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   1 /*
   2  * $RDCfile: $ $Revision: 1.1.2.6 $ $Date: 2007/11/28 17:15:18 $
   3  *******************************************************************************
   4  *
   5  * FIFO Generator - Verilog Behavioral Model
   6  *
   7  *******************************************************************************
   8  *
   9  * Copyright(C) 2006 by Xilinx, Inc. All rights reserved.
  10  * This text/file contains proprietary, confidential
  11  * information of Xilinx, Inc., is distributed under
  12  * license from Xilinx, Inc., and may be used, copied
  13  * and/or disclosed only pursuant to the terms of a valid
  14  * license agreement with Xilinx, Inc. Xilinx hereby
  15  * grants you a license to use this text/file solely for
  16  * design, simulation, implementation and creation of
  17  * design files limited to Xilinx devices or technologies.
  18  * Use with non-Xilinx devices or technologies is expressly
  19  * prohibited and immediately terminates your license unless
  20  * covered by a separate agreement.
  21  *
  22  * Xilinx is providing theis design, code, or information
  23  * "as-is" solely for use in developing programs and
  24  * solutions for Xilinx devices, with no obligation on the
  25  * part of Xilinx to provide support. By providing this design,
  26  * code, or information as one possible implementation of
  27  * this feature, application or standard. Xilinx is making no
  28  * representation that this implementation is free from any
  29  * claims of infringement. You are responsible for obtaining
  30  * any rights you may require for your implementation.
  31  * Xilinx expressly disclaims any warranty whatsoever with
  32  * respect to the adequacy of the implementation, including
  33  * but not limited to any warranties or representations that this
  34  * implementation is free from claims of infringement, implied
  35  * warranties of merchantability or fitness for a particular
  36  * purpose.
  37  *
  38  * Xilinx products are not intended for use in life support
  39  * appliances, devices, or systems. Use in such applications is
  40  * expressly prohibited.
  41  *
  42  * This copyright and support notice must be retained as part
  43  * of this text at all times. (c)Copyright 1995-2006 Xilinx, Inc.
  44  * All rights reserved.
  45  *
  46  *******************************************************************************
  47  *
  48  * Filename: FIFO_GENERATOR_V4_3.v
  49  *
  50  * Author     : Xilinx
  51  *
  52  *******************************************************************************
  53  * Structure:
  54  *
  55  * fifo_generator_v4_3.vhd
  56  *    |
  57  *    +-fifo_generator_v4_3_bhv_as
  58  *    |
  59  *    +-fifo_generator_v4_3_bhv_ss
  60  *    |
  61  *    +-fifo_generator_v4_3_bhv_preload0
  62  *
  63  *******************************************************************************
  64  * Description:
  65  *
  66  * The Verilog behavioral model for the FIFO Generator.
  67  *
  68  *   The behavioral model has three parts:
  69  *      - The behavioral model for independent clocks FIFOs (_as)
  70  *      - The behavioral model for common clock FIFOs (_ss)
  71  *      - The "preload logic" block which implements First-word Fall-through
  72  *
  73  *******************************************************************************
  74  * Description:
  75  *  The verilog behavioral model for the FIFO generator core.
  76  *
  77  *******************************************************************************
  78  */
  79
  80 `timescale 1ps/1ps
  81
  82 /*******************************************************************************
  83  * Declaration of top-level module
  84  ******************************************************************************/
  85 module FIFO_GENERATOR_V4_3
  86 (
  87   BACKUP, //not used
  88   BACKUP_MARKER, //not used
  89   CLK,
  90   DIN,
  91   PROG_EMPTY_THRESH,
  92   PROG_EMPTY_THRESH_ASSERT,
  93   PROG_EMPTY_THRESH_NEGATE,
  94   PROG_FULL_THRESH,
  95   PROG_FULL_THRESH_ASSERT,
  96   PROG_FULL_THRESH_NEGATE,
  97   RD_CLK,
  98   RD_EN,
  99   RD_RST, //not used
 100   RST,
 101   SRST,
 102   WR_CLK,
 103   WR_EN,
 104   WR_RST, //not used
 105   INT_CLK,
 106
 107   ALMOST_EMPTY,
 108   ALMOST_FULL,
 109   DATA_COUNT,
 110   DOUT,
 111   EMPTY,
 112   FULL,
 113   OVERFLOW,
 114   PROG_EMPTY,
 115   PROG_FULL,
 116   RD_DATA_COUNT,
 117   UNDERFLOW,
 118   VALID,
 119   WR_ACK,
 120   WR_DATA_COUNT,
 121
 122   SBITERR,
 123   DBITERR
 124   );
 125
 126 /*
 127  ******************************************************************************
 128  * Definition of Parameters
 129  ******************************************************************************
 130  *     C_COMMON_CLOCK                : Common Clock (1), Independent Clocks (0)
 131  *     C_COUNT_TYPE                  :    *not used
 132  *     C_DATA_COUNT_WIDTH            : Width of DATA_COUNT bus
 133  *     C_DEFAULT_VALUE               :    *not used
 134  *     C_DIN_WIDTH                   : Width of DIN bus
 135  *     C_DOUT_RST_VAL                : Reset value of DOUT
 136  *     C_DOUT_WIDTH                  : Width of DOUT bus
 137  *     C_ENABLE_RLOCS                :    *not used
 138  *     C_FAMILY                      : not used in bhv model
 139  *     C_FULL_FLAGS_RST_VAL          : Full flags rst val (0 or 1)
 140  *     C_HAS_ALMOST_EMPTY            : 1=Core has ALMOST_EMPTY flag
 141  *     C_HAS_ALMOST_FULL             : 1=Core has ALMOST_FULL flag
 142  *     C_HAS_BACKUP                  :    *not used
 143  *     C_HAS_DATA_COUNT              : 1=Core has DATA_COUNT bus
 144  *     C_HAS_INT_CLK                 : not used in bhv model
 145  *     C_HAS_MEMINIT_FILE            :    *not used
 146  *     C_HAS_OVERFLOW                : 1=Core has OVERFLOW flag
 147  *     C_HAS_RD_DATA_COUNT           : 1=Core has RD_DATA_COUNT bus
 148  *     C_HAS_RD_RST                  :    *not used
 149  *     C_HAS_RST                     : 1=Core has Async Rst
 150  *     C_HAS_SRST                    : 1=Core has Sync Rst
 151  *     C_HAS_UNDERFLOW               : 1=Core has UNDERFLOW flag
 152  *     C_HAS_VALID                   : 1=Core has VALID flag
 153  *     C_HAS_WR_ACK                  : 1=Core has WR_ACK flag
 154  *     C_HAS_WR_DATA_COUNT           : 1=Core has WR_DATA_COUNT bus
 155  *     C_HAS_WR_RST                  :    *not used
 156  *     C_IMPLEMENTATION_TYPE         : 0=Common-Clock Bram/Dram
 157  *                                     1=Common-Clock ShiftRam
 158  *                                     2=Indep. Clocks Bram/Dram
 159  *                                     3=Virtex-4 Built-in
 160  *                                     4=Virtex-5 Built-in
 161  *     C_INIT_WR_PNTR_VAL            :   *not used
 162  *     C_MEMORY_TYPE                 : 1=Block RAM
 163  *                                     2=Distributed RAM
 164  *                                     3=Shift RAM
 165  *                                     4=Built-in FIFO
 166  *     C_MIF_FILE_NAME               :   *not used
 167  *     C_OPTIMIZATION_MODE           :   *not used
 168  *     C_OVERFLOW_LOW                : 1=OVERFLOW active low
 169  *     C_PRELOAD_LATENCY             : Latency of read: 0, 1, 2
 170  *     C_PRELOAD_REGS                : 1=Use output registers
 171  *     C_PRIM_FIFO_TYPE              : not used in bhv model
 172  *     C_PROG_EMPTY_THRESH_ASSERT_VAL: PROG_EMPTY assert threshold
 173  *     C_PROG_EMPTY_THRESH_NEGATE_VAL: PROG_EMPTY negate threshold
 174  *     C_PROG_EMPTY_TYPE             : 0=No programmable empty
 175  *                                     1=Single prog empty thresh constant
 176  *                                     2=Multiple prog empty thresh constants
 177  *                                     3=Single prog empty thresh input
 178  *                                     4=Multiple prog empty thresh inputs
 179  *     C_PROG_FULL_THRESH_ASSERT_VAL : PROG_FULL assert threshold
 180  *     C_PROG_FULL_THRESH_NEGATE_VAL : PROG_FULL negate threshold
 181  *     C_PROG_FULL_TYPE              : 0=No prog full
 182  *                                     1=Single prog full thresh constant
 183  *                                     2=Multiple prog full thresh constants
 184  *                                     3=Single prog full thresh input
 185  *                                     4=Multiple prog full thresh inputs
 186  *     C_RD_DATA_COUNT_WIDTH         : Width of RD_DATA_COUNT bus
 187  *     C_RD_DEPTH                    : Depth of read interface (2^N)
 188  *     C_RD_FREQ                     : not used in bhv model
 189  *     C_RD_PNTR_WIDTH               : always log2(C_RD_DEPTH)
 190  *     C_UNDERFLOW_LOW               : 1=UNDERFLOW active low
 191  *     C_USE_DOUT_RST                : 1=Resets DOUT on RST
 192  *     C_USE_ECC                     : not used in bhv model
 193  *     C_USE_EMBEDDED_REG            : 1=Use BRAM embedded output register
 194  *     C_USE_FIFO16_FLAGS            : not used in bhv model
 195  *     C_USE_FWFT_DATA_COUNT         : 1=Use extra logic for FWFT data count
 196  *     C_VALID_LOW                   : 1=VALID active low
 197  *     C_WR_ACK_LOW                  : 1=WR_ACK active low
 198  *     C_WR_DATA_COUNT_WIDTH         : Width of WR_DATA_COUNT bus
 199  *     C_WR_DEPTH                    : Depth of write interface (2^N)
 200  *     C_WR_FREQ                     : not used in bhv model
 201  *     C_WR_PNTR_WIDTH               : always log2(C_WR_DEPTH)
 202  *     C_WR_RESPONSE_LATENCY         :    *not used
 203  *     C_MSGON_VAL                   :    *not used by bhv model
 204  ******************************************************************************
 205  * Definition of Ports
 206  ******************************************************************************
 207  *   BACKUP       : Not used
 208  *   BACKUP_MARKER: Not used
 209  *   CLK          : Clock
 210  *   DIN          : Input data bus
 211  *   PROG_EMPTY_THRESH       : Threshold for Programmable Empty Flag
 212  *   PROG_EMPTY_THRESH_ASSERT: Threshold for Programmable Empty Flag
 213  *   PROG_EMPTY_THRESH_NEGATE: Threshold for Programmable Empty Flag
 214  *   PROG_FULL_THRESH        : Threshold for Programmable Full Flag
 215  *   PROG_FULL_THRESH_ASSERT : Threshold for Programmable Full Flag
 216  *   PROG_FULL_THRESH_NEGATE : Threshold for Programmable Full Flag
 217  *   RD_CLK       : Read Domain Clock
 218  *   RD_EN        : Read enable
 219  *   RD_RST       : Not used
 220  *   RST          : Asynchronous Reset
 221  *   SRST         : Synchronous Reset
 222  *   WR_CLK       : Write Domain Clock
 223  *   WR_EN        : Write enable
 224  *   WR_RST       : Not used
 225  *   INT_CLK      : Internal Clock
 226  *   ALMOST_EMPTY : One word remaining in FIFO
 227  *   ALMOST_FULL  : One empty space remaining in FIFO
 228  *   DATA_COUNT   : Number of data words in fifo( synchronous to CLK)
 229  *   DOUT         : Output data bus
 230  *   EMPTY        : Empty flag
 231  *   FULL         : Full flag
 232  *   OVERFLOW     : Last write rejected
 233  *   PROG_EMPTY   : Programmable Empty Flag
 234  *   PROG_FULL    : Programmable Full Flag
 235  *   RD_DATA_COUNT: Number of data words in fifo (synchronous to RD_CLK)
 236  *   UNDERFLOW    : Last read rejected
 237  *   VALID        : Last read acknowledged, DOUT bus VALID
 238  *   WR_ACK       : Last write acknowledged
 239  *   WR_DATA_COUNT: Number of data words in fifo (synchronous to WR_CLK)
 240  *   SBITERR      : Single Bit ECC Error Detected
 241  *   DBITERR      : Double Bit ECC Error Detected
 242  ******************************************************************************
 243  */
 244
 245
 246   /****************************************************************************
 247   * Declare user parameters and their defaults
 248   *****************************************************************************/
 249   parameter  C_COMMON_CLOCK                 = 0;
 250   parameter  C_COUNT_TYPE                   = 0; //not used
 251   parameter  C_DATA_COUNT_WIDTH             = 2;
 252   parameter  C_DEFAULT_VALUE                = ""; //not used
 253   parameter  C_DIN_WIDTH                    = 8;
 254   parameter  C_DOUT_RST_VAL                 = "";
 255   parameter  C_DOUT_WIDTH                   = 8;
 256   parameter  C_ENABLE_RLOCS                 = 0; //not used
 257   parameter  C_FAMILY                       = "virtex2"; //not used in bhv model
 258   parameter  C_FULL_FLAGS_RST_VAL           = 1;
 259   parameter  C_HAS_ALMOST_EMPTY             = 0;
 260   parameter  C_HAS_ALMOST_FULL              = 0;
 261   parameter  C_HAS_BACKUP                   = 0; //not used
 262   parameter  C_HAS_DATA_COUNT               = 0;
 263   parameter  C_HAS_INT_CLK                  = 0; //not used in bhv model
 264   parameter  C_HAS_MEMINIT_FILE             = 0; //not used
 265   parameter  C_HAS_OVERFLOW                 = 0;
 266   parameter  C_HAS_RD_DATA_COUNT            = 0;
 267   parameter  C_HAS_RD_RST                   = 0; //not used
 268   parameter  C_HAS_RST                      = 0;
 269   parameter  C_HAS_SRST                     = 0;
 270   parameter  C_HAS_UNDERFLOW                = 0;
 271   parameter  C_HAS_VALID                    = 0;
 272   parameter  C_HAS_WR_ACK                   = 0;
 273   parameter  C_HAS_WR_DATA_COUNT            = 0;
 274   parameter  C_HAS_WR_RST                   = 0; //not used
 275   parameter  C_IMPLEMENTATION_TYPE          = 0;
 276   parameter  C_INIT_WR_PNTR_VAL             = 0; //not used
 277   parameter  C_MEMORY_TYPE                  = 1;
 278   parameter  C_MIF_FILE_NAME                = ""; //not used
 279   parameter  C_OPTIMIZATION_MODE            = 0; //not used
 280   parameter  C_OVERFLOW_LOW                 = 0;
 281   parameter  C_PRELOAD_LATENCY              = 1;
 282   parameter  C_PRELOAD_REGS                 = 0;
 283   parameter  C_PRIM_FIFO_TYPE               = 512; //not used in bhv model
 284   parameter  C_PROG_EMPTY_THRESH_ASSERT_VAL = 0;
 285   parameter  C_PROG_EMPTY_THRESH_NEGATE_VAL = 0;
 286   parameter  C_PROG_EMPTY_TYPE              = 0;
 287   parameter  C_PROG_FULL_THRESH_ASSERT_VAL  = 0;
 288   parameter  C_PROG_FULL_THRESH_NEGATE_VAL  = 0;
 289   parameter  C_PROG_FULL_TYPE               = 0;
 290   parameter  C_RD_DATA_COUNT_WIDTH          = 2;
 291   parameter  C_RD_DEPTH                     = 256;
 292   parameter  C_RD_FREQ                      = 1; //not used in bhv model
 293   parameter  C_RD_PNTR_WIDTH                = 8;
 294   parameter  C_UNDERFLOW_LOW                = 0;
 295   parameter  C_USE_DOUT_RST                 = 0;
 296   parameter  C_USE_ECC                      = 0; //not used in bhv model
 297   parameter  C_USE_EMBEDDED_REG             = 0;
 298   parameter  C_USE_FIFO16_FLAGS             = 0; //not used in bhv model
 299   parameter  C_USE_FWFT_DATA_COUNT          = 0;
 300   parameter  C_VALID_LOW                    = 0;
 301   parameter  C_WR_ACK_LOW                   = 0;
 302   parameter  C_WR_DATA_COUNT_WIDTH          = 2;
 303   parameter  C_WR_DEPTH                     = 256;
 304   parameter  C_WR_FREQ                      = 1; //not used in bhv model
 305   parameter  C_WR_PNTR_WIDTH                = 8;
 306   parameter  C_WR_RESPONSE_LATENCY          = 1; //not used
 307   parameter  C_MSGON_VAL                    = 1; //not used
 308
 309
 310
 311   /*****************************************************************************
 312    * Derived parameters
 313    ****************************************************************************/
 314   //There are 2 Verilog behavioral models
 315   // 0 = Common-Clock FIFO/ShiftRam FIFO
 316   // 1 = Independent Clocks FIFO
 317   parameter  C_VERILOG_IMPL = (C_IMPLEMENTATION_TYPE==0 ? 0 :
 318                                (C_IMPLEMENTATION_TYPE==1 ? 0 :
 319                                 (C_IMPLEMENTATION_TYPE==2 ? 1 : 0)));
 320
 321   /*****************************************************************************
 322    * Declare Input and Output Ports
 323    ****************************************************************************/
 324   input                              CLK;
 325   input                              BACKUP;
 326   input                              BACKUP_MARKER;
 327   input [C_DIN_WIDTH-1:0]            DIN;
 328   input [C_RD_PNTR_WIDTH-1:0]        PROG_EMPTY_THRESH;
 329   input [C_RD_PNTR_WIDTH-1:0]        PROG_EMPTY_THRESH_ASSERT;
 330   input [C_RD_PNTR_WIDTH-1:0]        PROG_EMPTY_THRESH_NEGATE;
 331   input [C_WR_PNTR_WIDTH-1:0]        PROG_FULL_THRESH;
 332   input [C_WR_PNTR_WIDTH-1:0]        PROG_FULL_THRESH_ASSERT;
 333   input [C_WR_PNTR_WIDTH-1:0]        PROG_FULL_THRESH_NEGATE;
 334   input                              RD_CLK;
 335   input                              RD_EN;
 336   input                              RD_RST;
 337   input                              RST;
 338   input                              SRST;
 339   input                              WR_CLK;
 340   input                              WR_EN;
 341   input                              WR_RST;
 342   input                              INT_CLK;
 343
 344   output                             ALMOST_EMPTY;
 345   output                             ALMOST_FULL;
 346   output [C_DATA_COUNT_WIDTH-1:0]    DATA_COUNT;
 347   output [C_DOUT_WIDTH-1:0]          DOUT;
 348   output                             EMPTY;
 349   output                             FULL;
 350   output                             OVERFLOW;
 351   output                             PROG_EMPTY;
 352   output                             PROG_FULL;
 353   output                             VALID;
 354   output [C_RD_DATA_COUNT_WIDTH-1:0] RD_DATA_COUNT;
 355   output                             UNDERFLOW;
 356   output                             WR_ACK;
 357   output [C_WR_DATA_COUNT_WIDTH-1:0] WR_DATA_COUNT;
 358   output                             SBITERR;
 359   output                             DBITERR;
 360
 361
 362   wire                               ALMOST_EMPTY;
 363   wire                               ALMOST_FULL;
 364   wire [C_DATA_COUNT_WIDTH-1:0]      DATA_COUNT;
 365   wire [C_DOUT_WIDTH-1:0]            DOUT;
 366   wire                               EMPTY;
 367   wire                               FULL;
 368   wire                               OVERFLOW;
 369   wire                               PROG_EMPTY;
 370   wire                               PROG_FULL;
 371   wire                               VALID;
 372   wire [C_RD_DATA_COUNT_WIDTH-1:0]   RD_DATA_COUNT;
 373   wire                               UNDERFLOW;
 374   wire                               WR_ACK;
 375   wire [C_WR_DATA_COUNT_WIDTH-1:0]   WR_DATA_COUNT;
 376
 377
 378   wire                               RD_CLK_P0_IN;
 379   wire                               RST_P0_IN;
 380   wire                               RD_EN_FIFO_IN;
 381   wire                               RD_EN_P0_IN;
 382
 383   wire                               ALMOST_EMPTY_FIFO_OUT;
 384   wire                               ALMOST_FULL_FIFO_OUT;
 385   wire [C_DATA_COUNT_WIDTH-1:0]      DATA_COUNT_FIFO_OUT;
 386   wire [C_DOUT_WIDTH-1:0]            DOUT_FIFO_OUT;
 387   wire                               EMPTY_FIFO_OUT;
 388   wire                               FULL_FIFO_OUT;
 389   wire                               OVERFLOW_FIFO_OUT;
 390   wire                               PROG_EMPTY_FIFO_OUT;
 391   wire                               PROG_FULL_FIFO_OUT;
 392   wire                               VALID_FIFO_OUT;
 393   wire [C_RD_DATA_COUNT_WIDTH-1:0]   RD_DATA_COUNT_FIFO_OUT;
 394   wire                               UNDERFLOW_FIFO_OUT;
 395   wire                               WR_ACK_FIFO_OUT;
 396   wire [C_WR_DATA_COUNT_WIDTH-1:0]   WR_DATA_COUNT_FIFO_OUT;
 397
 398
 399   //***************************************************************************
 400   // Internal Signals
 401   //   The core uses either the internal_ wires or the preload0_ wires depending
 402   //     on whether the core uses Preload0 or not.
 403   //   When using preload0, the internal signals connect the internal core to
 404   //     the preload logic, and the external core's interfaces are tied to the
 405   //     preload0 signals from the preload logic.
 406   //***************************************************************************
 407   wire [C_DOUT_WIDTH-1:0]            DATA_P0_OUT;
 408   wire                               VALID_P0_OUT;
 409   wire                               EMPTY_P0_OUT;
 410   wire                               ALMOSTEMPTY_P0_OUT;
 411   reg                                EMPTY_P0_OUT_Q;
 412   reg                                ALMOSTEMPTY_P0_OUT_Q;
 413   wire                               UNDERFLOW_P0_OUT;
 414   wire                               RDEN_P0_OUT;
 415   wire [C_DOUT_WIDTH-1:0]            DATA_P0_IN;
 416   wire                               EMPTY_P0_IN;
 417   reg  [31:0]      DATA_COUNT_FWFT;
 418   reg                               SS_FWFT_WR  ;
 419   reg                              SS_FWFT_RD ;
 420
 421   assign SBITERR = 1'b0;
 422   assign DBITERR = 1'b0;
 423
 424
 425 // Choose the behavioral model to instantiate based on the C_VERILOG_IMPL
 426 // parameter (1=Independent Clocks, 0=Common Clock)
 427 generate
 428 case (C_VERILOG_IMPL)
 429 0 : begin : block1
 430   //Common Clock Behavioral Model
 431   fifo_generator_v4_3_bhv_ver_ss
 432   #(
 433     C_DATA_COUNT_WIDTH,
 434     C_DIN_WIDTH,
 435     C_DOUT_RST_VAL,
 436     C_DOUT_WIDTH,
 437     C_FULL_FLAGS_RST_VAL,
 438     C_HAS_ALMOST_EMPTY,
 439     C_HAS_ALMOST_FULL,
 440     C_HAS_DATA_COUNT,
 441     C_HAS_OVERFLOW,
 442     C_HAS_RD_DATA_COUNT,
 443     C_HAS_RST,
 444     C_HAS_SRST,
 445     C_HAS_UNDERFLOW,
 446     C_HAS_VALID,
 447     C_HAS_WR_ACK,
 448     C_HAS_WR_DATA_COUNT,
 449     C_IMPLEMENTATION_TYPE,
 450     C_MEMORY_TYPE,
 451     C_OVERFLOW_LOW,
 452     C_PRELOAD_LATENCY,
 453     C_PRELOAD_REGS,
 454     C_PROG_EMPTY_THRESH_ASSERT_VAL,
 455     C_PROG_EMPTY_THRESH_NEGATE_VAL,
 456     C_PROG_EMPTY_TYPE,
 457     C_PROG_FULL_THRESH_ASSERT_VAL,
 458     C_PROG_FULL_THRESH_NEGATE_VAL,
 459     C_PROG_FULL_TYPE,
 460     C_RD_DATA_COUNT_WIDTH,
 461     C_RD_DEPTH,
 462     C_RD_PNTR_WIDTH,
 463     C_UNDERFLOW_LOW,
 464     C_USE_DOUT_RST,
 465     C_USE_EMBEDDED_REG,
 466     C_USE_FWFT_DATA_COUNT,
 467     C_VALID_LOW,
 468     C_WR_ACK_LOW,
 469     C_WR_DATA_COUNT_WIDTH,
 470     C_WR_DEPTH,
 471     C_WR_PNTR_WIDTH
 472   )
 473   gen_ss
 474   (
 475     .CLK                      (CLK),
 476     .RST                      (RST),
 477     .SRST                     (SRST),
 478     .DIN                      (DIN),
 479     .WR_EN                    (WR_EN),
 480     .RD_EN                    (RD_EN_FIFO_IN),
 481     .PROG_EMPTY_THRESH        (PROG_EMPTY_THRESH),
 482     .PROG_EMPTY_THRESH_ASSERT (PROG_EMPTY_THRESH_ASSERT),
 483     .PROG_EMPTY_THRESH_NEGATE (PROG_EMPTY_THRESH_NEGATE),
 484     .PROG_FULL_THRESH         (PROG_FULL_THRESH),
 485     .PROG_FULL_THRESH_ASSERT  (PROG_FULL_THRESH_ASSERT),
 486     .PROG_FULL_THRESH_NEGATE  (PROG_FULL_THRESH_NEGATE),
 487     .DOUT                     (DOUT_FIFO_OUT),
 488     .FULL                     (FULL_FIFO_OUT),
 489     .ALMOST_FULL              (ALMOST_FULL_FIFO_OUT),
 490     .WR_ACK                   (WR_ACK_FIFO_OUT),
 491     .OVERFLOW                 (OVERFLOW_FIFO_OUT),
 492     .EMPTY                    (EMPTY_FIFO_OUT),
 493     .ALMOST_EMPTY             (ALMOST_EMPTY_FIFO_OUT),
 494     .VALID                    (VALID_FIFO_OUT),
 495     .UNDERFLOW                (UNDERFLOW_FIFO_OUT),
 496     .DATA_COUNT               (DATA_COUNT_FIFO_OUT),
 497     .PROG_FULL                (PROG_FULL_FIFO_OUT),
 498     .PROG_EMPTY               (PROG_EMPTY_FIFO_OUT)
 499    );
 500 end
 501 1 : begin : block1
 502   //Independent Clocks Behavioral Model
 503   fifo_generator_v4_3_bhv_ver_as
 504   #(
 505     C_DATA_COUNT_WIDTH,
 506     C_DIN_WIDTH,
 507     C_DOUT_RST_VAL,
 508     C_DOUT_WIDTH,
 509     C_FULL_FLAGS_RST_VAL,
 510     C_HAS_ALMOST_EMPTY,
 511     C_HAS_ALMOST_FULL,
 512     C_HAS_DATA_COUNT,
 513     C_HAS_OVERFLOW,
 514     C_HAS_RD_DATA_COUNT,
 515     C_HAS_RST,
 516     C_HAS_UNDERFLOW,
 517     C_HAS_VALID,
 518     C_HAS_WR_ACK,
 519     C_HAS_WR_DATA_COUNT,
 520     C_IMPLEMENTATION_TYPE,
 521     C_MEMORY_TYPE,
 522     C_OVERFLOW_LOW,
 523     C_PRELOAD_LATENCY,
 524     C_PRELOAD_REGS,
 525     C_PROG_EMPTY_THRESH_ASSERT_VAL,
 526     C_PROG_EMPTY_THRESH_NEGATE_VAL,
 527     C_PROG_EMPTY_TYPE,
 528     C_PROG_FULL_THRESH_ASSERT_VAL,
 529     C_PROG_FULL_THRESH_NEGATE_VAL,
 530     C_PROG_FULL_TYPE,
 531     C_RD_DATA_COUNT_WIDTH,
 532     C_RD_DEPTH,
 533     C_RD_PNTR_WIDTH,
 534     C_UNDERFLOW_LOW,
 535     C_USE_DOUT_RST,
 536     C_USE_EMBEDDED_REG,
 537     C_USE_FWFT_DATA_COUNT,
 538     C_VALID_LOW,
 539     C_WR_ACK_LOW,
 540     C_WR_DATA_COUNT_WIDTH,
 541     C_WR_DEPTH,
 542     C_WR_PNTR_WIDTH
 543   )
 544   gen_as
 545   (
 546     .WR_CLK                   (WR_CLK),
 547     .RD_CLK                   (RD_CLK),
 548     .RST                      (RST),
 549     .DIN                      (DIN),
 550     .WR_EN                    (WR_EN),
 551     .RD_EN                    (RD_EN_FIFO_IN),
 552     .PROG_EMPTY_THRESH        (PROG_EMPTY_THRESH),
 553     .PROG_EMPTY_THRESH_ASSERT (PROG_EMPTY_THRESH_ASSERT),
 554     .PROG_EMPTY_THRESH_NEGATE (PROG_EMPTY_THRESH_NEGATE),
 555     .PROG_FULL_THRESH         (PROG_FULL_THRESH),
 556     .PROG_FULL_THRESH_ASSERT  (PROG_FULL_THRESH_ASSERT),
 557     .PROG_FULL_THRESH_NEGATE  (PROG_FULL_THRESH_NEGATE),
 558     .DOUT                     (DOUT_FIFO_OUT),
 559     .FULL                     (FULL_FIFO_OUT),
 560     .ALMOST_FULL              (ALMOST_FULL_FIFO_OUT),
 561     .WR_ACK                   (WR_ACK_FIFO_OUT),
 562     .OVERFLOW                 (OVERFLOW_FIFO_OUT),
 563     .EMPTY                    (EMPTY_FIFO_OUT),
 564     .ALMOST_EMPTY             (ALMOST_EMPTY_FIFO_OUT),
 565     .VALID                    (VALID_FIFO_OUT),
 566     .UNDERFLOW                (UNDERFLOW_FIFO_OUT),
 567     .RD_DATA_COUNT            (RD_DATA_COUNT_FIFO_OUT),
 568     .WR_DATA_COUNT            (WR_DATA_COUNT_FIFO_OUT),
 569     .PROG_FULL                (PROG_FULL_FIFO_OUT),
 570     .PROG_EMPTY               (PROG_EMPTY_FIFO_OUT)
 571    );
 572 end
 573
 574 default : begin : block1
 575   //Independent Clocks Behavioral Model
 576   fifo_generator_v4_3_bhv_ver_as
 577   #(
 578     C_DATA_COUNT_WIDTH,
 579     C_DIN_WIDTH,
 580     C_DOUT_RST_VAL,
 581     C_DOUT_WIDTH,
 582     C_FULL_FLAGS_RST_VAL,
 583     C_HAS_ALMOST_EMPTY,
 584     C_HAS_ALMOST_FULL,
 585     C_HAS_DATA_COUNT,
 586     C_HAS_OVERFLOW,
 587     C_HAS_RD_DATA_COUNT,
 588     C_HAS_RST,
 589     C_HAS_UNDERFLOW,
 590     C_HAS_VALID,
 591     C_HAS_WR_ACK,
 592     C_HAS_WR_DATA_COUNT,
 593     C_IMPLEMENTATION_TYPE,
 594     C_MEMORY_TYPE,
 595     C_OVERFLOW_LOW,
 596     C_PRELOAD_LATENCY,
 597     C_PRELOAD_REGS,
 598     C_PROG_EMPTY_THRESH_ASSERT_VAL,
 599     C_PROG_EMPTY_THRESH_NEGATE_VAL,
 600     C_PROG_EMPTY_TYPE,
 601     C_PROG_FULL_THRESH_ASSERT_VAL,
 602     C_PROG_FULL_THRESH_NEGATE_VAL,
 603     C_PROG_FULL_TYPE,
 604     C_RD_DATA_COUNT_WIDTH,
 605     C_RD_DEPTH,
 606     C_RD_PNTR_WIDTH,
 607     C_UNDERFLOW_LOW,
 608     C_USE_DOUT_RST,
 609     C_USE_EMBEDDED_REG,
 610     C_USE_FWFT_DATA_COUNT,
 611     C_VALID_LOW,
 612     C_WR_ACK_LOW,
 613     C_WR_DATA_COUNT_WIDTH,
 614     C_WR_DEPTH,
 615     C_WR_PNTR_WIDTH
 616   )
 617   gen_as
 618   (
 619     .WR_CLK                   (WR_CLK),
 620     .RD_CLK                   (RD_CLK),
 621     .RST                      (RST),
 622     .DIN                      (DIN),
 623     .WR_EN                    (WR_EN),
 624     .RD_EN                    (RD_EN_FIFO_IN),
 625     .PROG_EMPTY_THRESH        (PROG_EMPTY_THRESH),
 626     .PROG_EMPTY_THRESH_ASSERT (PROG_EMPTY_THRESH_ASSERT),
 627     .PROG_EMPTY_THRESH_NEGATE (PROG_EMPTY_THRESH_NEGATE),
 628     .PROG_FULL_THRESH         (PROG_FULL_THRESH),
 629     .PROG_FULL_THRESH_ASSERT  (PROG_FULL_THRESH_ASSERT),
 630     .PROG_FULL_THRESH_NEGATE  (PROG_FULL_THRESH_NEGATE),
 631     .DOUT                     (DOUT_FIFO_OUT),
 632     .FULL                     (FULL_FIFO_OUT),
 633     .ALMOST_FULL              (ALMOST_FULL_FIFO_OUT),
 634     .WR_ACK                   (WR_ACK_FIFO_OUT),
 635     .OVERFLOW                 (OVERFLOW_FIFO_OUT),
 636     .EMPTY                    (EMPTY_FIFO_OUT),
 637     .ALMOST_EMPTY             (ALMOST_EMPTY_FIFO_OUT),
 638     .VALID                    (VALID_FIFO_OUT),
 639     .UNDERFLOW                (UNDERFLOW_FIFO_OUT),
 640     .RD_DATA_COUNT            (RD_DATA_COUNT_FIFO_OUT),
 641     .WR_DATA_COUNT            (WR_DATA_COUNT_FIFO_OUT),
 642     .PROG_FULL                (PROG_FULL_FIFO_OUT),
 643     .PROG_EMPTY               (PROG_EMPTY_FIFO_OUT)
 644    );
 645 end
 646
 647 endcase
 648 endgenerate
 649
 650
 651    //**************************************************************************
 652    // Connect Internal Signals
 653    //   (Signals labeled internal_*)
 654    //  In the normal case, these signals tie directly to the FIFO's inputs and
 655    //    outputs.
 656    //  In the case of Preload Latency 0 or 1, there are intermediate
 657    //    signals between the internal FIFO and the preload logic.
 658    //**************************************************************************
 659
 660
 661    //***********************************************
 662    // If First-Word Fall-Through, instantiate
 663    // the preload0 (FWFT) module
 664    //***********************************************
 665    generate
 666       if (C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0) begin : block2
 667
 668
 669          fifo_generator_v4_3_bhv_ver_preload0
 670            #(
 671              C_DOUT_RST_VAL,
 672              C_DOUT_WIDTH,
 673              C_HAS_RST,
 674              C_USE_DOUT_RST,
 675              C_VALID_LOW,
 676              C_UNDERFLOW_LOW
 677              )
 678              fgpl0
 679                (
 680                 .RD_CLK           (RD_CLK_P0_IN),
 681                 .RD_RST           (RST_P0_IN),
 682                 .RD_EN            (RD_EN_P0_IN),
 683                 .FIFOEMPTY        (EMPTY_P0_IN),
 684                 .FIFODATA         (DATA_P0_IN),
 685                 .USERDATA         (DATA_P0_OUT),
 686                 .USERVALID        (VALID_P0_OUT),
 687                 .USEREMPTY        (EMPTY_P0_OUT),
 688                 .USERALMOSTEMPTY  (ALMOSTEMPTY_P0_OUT),
 689                 .USERUNDERFLOW    (UNDERFLOW_P0_OUT),
 690                 .RAMVALID         (RAMVALID_P0_OUT),
 691                 .FIFORDEN         (RDEN_P0_OUT)
 692                 );
 693
 694
 695          //***********************************************
 696          // Connect inputs to preload (FWFT) module
 697          //***********************************************
 698          //Connect the RD_CLK of the Preload (FWFT) module to CLK if we
 699          // have a common-clock FIFO, or RD_CLK if we have an
 700          // independent clock FIFO
 701          assign RD_CLK_P0_IN       = ((C_VERILOG_IMPL == 0) ? CLK : RD_CLK);
 702          assign RST_P0_IN          = RST;
 703          assign RD_EN_P0_IN        = RD_EN;
 704          assign EMPTY_P0_IN        = EMPTY_FIFO_OUT;
 705          assign DATA_P0_IN         = DOUT_FIFO_OUT;
 706
 707          //***********************************************
 708          // Connect outputs from preload (FWFT) module
 709          //***********************************************
 710          assign DOUT               = DATA_P0_OUT;
 711          assign VALID              = VALID_P0_OUT ;
 712          assign EMPTY              = EMPTY_P0_OUT;
 713          assign ALMOST_EMPTY       = ALMOSTEMPTY_P0_OUT;
 714          assign UNDERFLOW          = UNDERFLOW_P0_OUT ;
 715
 716          assign RD_EN_FIFO_IN      = RDEN_P0_OUT;
 717
 718
 719          //***********************************************
 720          // Create DATA_COUNT from First-Word Fall-Through
 721          // data count
 722          //***********************************************
 723          assign DATA_COUNT = (C_DATA_COUNT_WIDTH>C_RD_PNTR_WIDTH) ?
 724            DATA_COUNT_FWFT[C_RD_PNTR_WIDTH:0] :
 725            DATA_COUNT_FWFT[C_RD_PNTR_WIDTH:C_RD_PNTR_WIDTH-C_DATA_COUNT_WIDTH+1];
 726
 727          //***********************************************
 728          // Create DATA_COUNT from First-Word Fall-Through
 729          // data count
 730          //***********************************************
 731          always @ (posedge RD_CLK or posedge RST) begin
 732             if (RST) begin
 733                EMPTY_P0_OUT_Q       <= 1;
 734                ALMOSTEMPTY_P0_OUT_Q <= 1;
 735             end else begin
 736                EMPTY_P0_OUT_Q       <= EMPTY_P0_OUT;
 737                ALMOSTEMPTY_P0_OUT_Q <= ALMOSTEMPTY_P0_OUT;
 738             end
 739          end //always
 740
 741
 742          //***********************************************
 743          // logic for common-clock data count when FWFT is selected
 744          //***********************************************
 745          initial begin
 746             SS_FWFT_RD = 1'b0;
 747             DATA_COUNT_FWFT = 0 ;
 748             SS_FWFT_WR   = 1'b0 ;
 749          end //initial
 750
 751
 752          //***********************************************
 753          // common-clock data count is implemented as an
 754          // up-down counter. SS_FWFT_WR and SS_FWFT_RD
 755          // are the up/down enables for the counter.
 756          //***********************************************
 757          always @ (RD_EN or VALID_P0_OUT or WR_EN or FULL_FIFO_OUT) begin
 758             SS_FWFT_RD = RD_EN && VALID_P0_OUT ;
 759             SS_FWFT_WR = (WR_EN && (~FULL_FIFO_OUT))  ;
 760          end
 761
 762          //***********************************************
 763          // common-clock data count is implemented as an
 764          // up-down counter for FWFT. This always block
 765          // calculates the counter.
 766          //***********************************************
 767          always @ (posedge RD_CLK_P0_IN or posedge RST) begin
 768             if (RST && (C_HAS_RST == 1) ) begin
 769                DATA_COUNT_FWFT      <= 0;
 770             end else begin
 771                if (SRST && (C_HAS_SRST == 1) ) begin
 772                   DATA_COUNT_FWFT      <= 0;
 773                end else begin
 774                   case ( {SS_FWFT_WR, SS_FWFT_RD})
 775                     2'b00: DATA_COUNT_FWFT <= DATA_COUNT_FWFT ;
 776                     2'b01: DATA_COUNT_FWFT <= DATA_COUNT_FWFT - 1 ;
 777                     2'b10: DATA_COUNT_FWFT <= DATA_COUNT_FWFT + 1 ;
 778                     2'b11: DATA_COUNT_FWFT <= DATA_COUNT_FWFT ;
 779                   endcase
 780                end //if SRST
 781             end //IF RST
 782          end //always
 783
 784
 785       end else begin : block2 //if !(C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0)
 786
 787          //***********************************************
 788          // If NOT First-Word Fall-Through, wire the outputs
 789          // of the internal _ss or _as FIFO directly to the
 790          // output, and do not instantiate the preload0
 791          // module.
 792          //***********************************************
 793
 794          assign RD_CLK_P0_IN       = 0;
 795          assign RST_P0_IN          = 0;
 796          assign RD_EN_P0_IN        = 0;
 797
 798          assign RD_EN_FIFO_IN      = RD_EN;
 799
 800          assign DOUT               = DOUT_FIFO_OUT;
 801          assign DATA_P0_IN         = 0;
 802          assign VALID              = VALID_FIFO_OUT;
 803          assign EMPTY              = EMPTY_FIFO_OUT;
 804          assign ALMOST_EMPTY       = ALMOST_EMPTY_FIFO_OUT;
 805          assign EMPTY_P0_IN        = 0;
 806          assign UNDERFLOW          = UNDERFLOW_FIFO_OUT;
 807          assign DATA_COUNT         = DATA_COUNT_FIFO_OUT;
 808
 809       end //if !(C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0)
 810    endgenerate
 811
 812
 813    //***********************************************
 814    // Connect user flags to internal signals
 815    //***********************************************
 816
 817    //If we are using extra logic for the FWFT data count, then override the
 818    //RD_DATA_COUNT output when we are EMPTY or ALMOST_EMPTY.
 819    //RD_DATA_COUNT is 0 when EMPTY and 1 when ALMOST_EMPTY.
 820    generate
 821       if (C_USE_FWFT_DATA_COUNT==1 && (C_RD_DATA_COUNT_WIDTH>C_RD_PNTR_WIDTH) ) begin : block3
 822          assign RD_DATA_COUNT = (EMPTY_P0_OUT_Q | RST) ? 0 : (ALMOSTEMPTY_P0_OUT_Q ? 1 : RD_DATA_COUNT_FIFO_OUT);
 823       end //block3
 824    endgenerate
 825
 826    //If we are using extra logic for the FWFT data count, then override the
 827    //RD_DATA_COUNT output when we are EMPTY or ALMOST_EMPTY.
 828    //Due to asymmetric ports, RD_DATA_COUNT is 0 when EMPTY or ALMOST_EMPTY.
 829    generate
 830       if (C_USE_FWFT_DATA_COUNT==1 && (C_RD_DATA_COUNT_WIDTH <=C_RD_PNTR_WIDTH) ) begin : block30
 831          assign RD_DATA_COUNT = (EMPTY_P0_OUT_Q | RST) ? 0 : (ALMOSTEMPTY_P0_OUT_Q ? 0 : RD_DATA_COUNT_FIFO_OUT);
 832       end //block30
 833    endgenerate
 834
 835    //If we are not using extra logic for the FWFT data count,
 836    //then connect RD_DATA_COUNT to the RD_DATA_COUNT from the
 837    //internal FIFO instance
 838    generate
 839       if (C_USE_FWFT_DATA_COUNT==0 ) begin : block31
 840          assign RD_DATA_COUNT = RD_DATA_COUNT_FIFO_OUT;
 841       end
 842    endgenerate
 843
 844    //Always connect WR_DATA_COUNT to the WR_DATA_COUNT from the internal
 845    //FIFO instance
 846    generate
 847       if (C_USE_FWFT_DATA_COUNT==1) begin : block4
 848          assign WR_DATA_COUNT = WR_DATA_COUNT_FIFO_OUT;
 849       end
 850       else begin : block4
 851          assign WR_DATA_COUNT = WR_DATA_COUNT_FIFO_OUT;
 852       end
 853    endgenerate
 854
 855
 856    //Connect other flags to the internal FIFO instance
 857    assign       FULL        = FULL_FIFO_OUT;
 858    assign       ALMOST_FULL = ALMOST_FULL_FIFO_OUT;
 859    assign       WR_ACK      = WR_ACK_FIFO_OUT;
 860    assign       OVERFLOW    = OVERFLOW_FIFO_OUT;
 861    assign       PROG_FULL   = PROG_FULL_FIFO_OUT;
 862    assign       PROG_EMPTY  = PROG_EMPTY_FIFO_OUT;
 863
 864
 865    // if an asynchronous FIFO has been selected, display a message that the FIFO
 866    //   will not be cycle-accurate in simulation
 867    initial begin
 868       if (C_IMPLEMENTATION_TYPE == 2) begin
 869          $display("Warning in %m at time %t: When using an asynchronous configuration for the FIFO Generator, the behavioral model is not cycle-accurate. You may wish to choose the structural simulation model instead of the behavioral model. This will ensure accurate behavior and latencies during simulation. You can enable this from CORE Generator by selecting Project -> Project Options -> Generation tab -> Structural Simulation. See the FIFO Generator User Guide for more information.", $time);
 870       end else if (C_IMPLEMENTATION_TYPE == 3 || C_IMPLEMENTATION_TYPE == 4) begin
 871          $display("Failure in %m at time %t: Use of Virtex-4 and Virtex-5 built-in FIFO configurations is currently not supported. Please use the structural simulation model. You can enable this from CORE Generator by selecting Project -> Project Options -> Generation tab -> Structural Simulation. See the FIFO Generator User Guide for more information.", $time);
 872          $finish;
 873       end
 874    end //initial
 875
 876 endmodule //FIFO_GENERATOR_V4_3
 877
 878
 879
 880 /*******************************************************************************
 881  * Declaration of Independent-Clocks FIFO Module
 882  ******************************************************************************/
 883 module fifo_generator_v4_3_bhv_ver_as
 884   (
 885    WR_CLK, RD_CLK, RST, DIN, WR_EN, RD_EN,
 886    PROG_EMPTY_THRESH, PROG_EMPTY_THRESH_ASSERT, PROG_EMPTY_THRESH_NEGATE,
 887    PROG_FULL_THRESH, PROG_FULL_THRESH_ASSERT, PROG_FULL_THRESH_NEGATE,
 888    DOUT, FULL, ALMOST_FULL, WR_ACK, OVERFLOW, EMPTY, ALMOST_EMPTY, VALID,
 889    UNDERFLOW, RD_DATA_COUNT, WR_DATA_COUNT, PROG_FULL, PROG_EMPTY
 890    );
 891
 892    /***************************************************************************
 893     * Declare user parameters and their defaults
 894     ***************************************************************************/
 895    parameter  C_DATA_COUNT_WIDTH             = 2;
 896    parameter  C_DIN_WIDTH                    = 8;
 897    parameter  C_DOUT_RST_VAL                 = "";
 898    parameter  C_DOUT_WIDTH                   = 8;
 899    parameter  C_FULL_FLAGS_RST_VAL           = 1;
 900    parameter  C_HAS_ALMOST_EMPTY             = 0;
 901    parameter  C_HAS_ALMOST_FULL              = 0;
 902    parameter  C_HAS_DATA_COUNT               = 0;
 903    parameter  C_HAS_OVERFLOW                 = 0;
 904    parameter  C_HAS_RD_DATA_COUNT            = 0;
 905    parameter  C_HAS_RST                      = 0;
 906    parameter  C_HAS_UNDERFLOW                = 0;
 907    parameter  C_HAS_VALID                    = 0;
 908    parameter  C_HAS_WR_ACK                   = 0;
 909    parameter  C_HAS_WR_DATA_COUNT            = 0;
 910    parameter  C_IMPLEMENTATION_TYPE          = 0;
 911    parameter  C_MEMORY_TYPE                  = 1;
 912    parameter  C_OVERFLOW_LOW                 = 0;
 913    parameter  C_PRELOAD_LATENCY              = 1;
 914    parameter  C_PRELOAD_REGS                 = 0;
 915    parameter  C_PROG_EMPTY_THRESH_ASSERT_VAL = 0;
 916    parameter  C_PROG_EMPTY_THRESH_NEGATE_VAL = 0;
 917    parameter  C_PROG_EMPTY_TYPE              = 0;
 918    parameter  C_PROG_FULL_THRESH_ASSERT_VAL  = 0;
 919    parameter  C_PROG_FULL_THRESH_NEGATE_VAL  = 0;
 920    parameter  C_PROG_FULL_TYPE               = 0;
 921    parameter  C_RD_DATA_COUNT_WIDTH          = 2;
 922    parameter  C_RD_DEPTH                     = 256;
 923    parameter  C_RD_PNTR_WIDTH                = 8;
 924    parameter  C_UNDERFLOW_LOW                = 0;
 925    parameter  C_USE_DOUT_RST                 = 0;
 926    parameter  C_USE_EMBEDDED_REG             = 0;
 927    parameter  C_USE_FWFT_DATA_COUNT          = 0;
 928    parameter  C_VALID_LOW                    = 0;
 929    parameter  C_WR_ACK_LOW                   = 0;
 930    parameter  C_WR_DATA_COUNT_WIDTH          = 2;
 931    parameter  C_WR_DEPTH                     = 256;
 932    parameter  C_WR_PNTR_WIDTH                = 8;
 933
 934    /***************************************************************************
 935     * Declare Input and Output Ports
 936     ***************************************************************************/
 937    input [C_DIN_WIDTH-1:0] DIN;
 938    input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH;
 939    input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_ASSERT;
 940    input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_NEGATE;
 941    input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH;
 942    input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_ASSERT;
 943    input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_NEGATE;
 944    input                       RD_CLK;
 945    input                       RD_EN;
 946    input                       RST;
 947    input                       WR_CLK;
 948    input                       WR_EN;
 949    output                      ALMOST_EMPTY;
 950    output                      ALMOST_FULL;
 951    output [C_DOUT_WIDTH-1:0]   DOUT;
 952    output                      EMPTY;
 953    output                      FULL;
 954    output                      OVERFLOW;
 955    output                      PROG_EMPTY;
 956    output                      PROG_FULL;
 957    output                      VALID;
 958    output [C_RD_DATA_COUNT_WIDTH-1:0] RD_DATA_COUNT;
 959    output                             UNDERFLOW;
 960    output                             WR_ACK;
 961    output [C_WR_DATA_COUNT_WIDTH-1:0] WR_DATA_COUNT;
 962
 963   /*************************************************************************
 964    * Declare the type for each Input/Output port, and connect each I/O
 965    * to it's associated internal signal in the behavioral model
 966    *
 967    * The values for the outputs are assigned in assign statements immediately
 968    * following wire, parameter, and function declarations in this code.
 969    *************************************************************************/
 970    //Inputs
 971    wire [C_DIN_WIDTH-1:0] DIN;
 972    wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH;
 973    wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_ASSERT;
 974    wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_NEGATE;
 975    wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH;
 976    wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_ASSERT;
 977    wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_NEGATE;
 978    wire RD_CLK;
 979    wire RD_EN;
 980    wire RST;
 981    wire WR_CLK;
 982    wire WR_EN;
 983
 984    //Outputs
 985    wire ALMOST_EMPTY;
 986    wire ALMOST_FULL;
 987    wire [C_DOUT_WIDTH-1:0] DOUT;
 988    wire EMPTY;
 989    wire FULL;
 990    wire OVERFLOW;
 991    wire PROG_EMPTY;
 992    wire PROG_FULL;
 993    wire VALID;
 994    wire [C_RD_DATA_COUNT_WIDTH-1:0] RD_DATA_COUNT;
 995    wire UNDERFLOW;
 996    wire WR_ACK;
 997    wire [C_WR_DATA_COUNT_WIDTH-1:0] WR_DATA_COUNT;
 998
 999
1000    /***************************************************************************
1001     * Parameters used as constants
1002     **************************************************************************/
1003    //When RST is present, set FULL reset value to '1'.
1004    //If core has no RST, make sure FULL powers-on as '0'.
1005    parameter C_DEPTH_RATIO_WR =
1006       (C_WR_DEPTH>C_RD_DEPTH) ? (C_WR_DEPTH/C_RD_DEPTH) : 1;
1007    parameter C_DEPTH_RATIO_RD =
1008       (C_RD_DEPTH>C_WR_DEPTH) ? (C_RD_DEPTH/C_WR_DEPTH) : 1;
1009    parameter C_FIFO_WR_DEPTH = C_WR_DEPTH - 1;
1010    parameter C_FIFO_RD_DEPTH = C_RD_DEPTH - 1;
1011
1012
1013    // EXTRA_WORDS = 2 * C_DEPTH_RATIO_WR / C_DEPTH_RATIO_RD
1014    // WR_DEPTH : RD_DEPTH = 1:2 => EXTRA_WORDS = 1
1015    // WR_DEPTH : RD_DEPTH = 1:4 => EXTRA_WORDS = 1 (rounded to ceiling)
1016    // WR_DEPTH : RD_DEPTH = 2:1 => EXTRA_WORDS = 4
1017    // WR_DEPTH : RD_DEPTH = 4:1 => EXTRA_WORDS = 8
1018    parameter EXTRA_WORDS = (C_DEPTH_RATIO_RD > 1)? 1:(2 * C_DEPTH_RATIO_WR);
1019    // extra_words_dc = 2 * C_DEPTH_RATIO_WR / C_DEPTH_RATIO_RD
1020    //  C_DEPTH_RATIO_WR | C_DEPTH_RATIO_RD | C_PNTR_WIDTH    | EXTRA_WORDS_DC
1021    //  -----------------|------------------|-----------------|---------------
1022    //  1                | 8                | C_RD_PNTR_WIDTH | 0
1023    //  1                | 4                | C_RD_PNTR_WIDTH | 0
1024    //  1                | 2                | C_RD_PNTR_WIDTH | 1
1025    //  1                | 1                | C_WR_PNTR_WIDTH | 2
1026    //  2                | 1                | C_WR_PNTR_WIDTH | 4
1027    //  4                | 1                | C_WR_PNTR_WIDTH | 8
1028    //  8                | 1                | C_WR_PNTR_WIDTH | 16
1029    parameter EXTRA_WORDS_DC = ( C_DEPTH_RATIO_RD > 2)?
1030                               0:(2 * C_DEPTH_RATIO_WR/C_DEPTH_RATIO_RD);
1031
1032
1033    parameter [31:0] reads_per_write = C_DIN_WIDTH/C_DOUT_WIDTH;
1034
1035    parameter [31:0] log2_reads_per_write = log2_val(reads_per_write);
1036
1037    parameter [31:0] writes_per_read = C_DOUT_WIDTH/C_DIN_WIDTH;
1038
1039    parameter [31:0] log2_writes_per_read = log2_val(writes_per_read);
1040
1041
1042
1043    /**************************************************************************
1044     * FIFO Contents Tracking and Data Count Calculations
1045     *************************************************************************/
1046
1047    //Memory which will be used to simulate a FIFO
1048    reg [C_DIN_WIDTH-1:0] memory[C_WR_DEPTH-1:0];
1049
1050    //The amount of data stored in the FIFO at any time is given
1051    // by num_wr_bits (in the WR_CLK domain) and num_rd_bits (in the RD_CLK
1052    // domain.
1053    //num_wr_bits is calculated by considering the total words in the FIFO,
1054    // and the state of the read pointer (which may not have yet crossed clock
1055    // domains.)
1056    //num_rd_bits is calculated by considering the total words in the FIFO,
1057    // and the state of the write pointer (which may not have yet crossed clock
1058    // domains.)
1059    reg [31:0]  num_wr_bits;
1060    reg [31:0]  num_rd_bits;
1061    reg [31:0]  next_num_wr_bits;
1062    reg [31:0]  next_num_rd_bits;
1063
1064    //The write pointer - tracks write operations
1065    // (Works opposite to core: wr_ptr is a DOWN counter)
1066    reg [31:0]  wr_ptr;
1067
1068    //The read pointer - tracks read operations
1069    // (Works opposite to core: rd_ptr is a DOWN counter)
1070    reg [31:0]  rd_ptr;
1071
1072    //Pointers passed into opposite clock domain
1073    reg [31:0]  wr_ptr_rdclk;
1074    reg [31:0]  wr_ptr_rdclk_next;
1075    reg [31:0]  rd_ptr_wrclk;
1076    reg [31:0]  rd_ptr_wrclk_next;
1077
1078    //Amount of data stored in the FIFO scaled to the narrowest (deepest) port
1079    // (Do not include data in FWFT stages)
1080    //Used to calculate PROG_EMPTY.
1081    wire [31:0] num_read_words_pe =
1082      num_rd_bits/(C_DOUT_WIDTH/C_DEPTH_RATIO_WR);
1083
1084    //Amount of data stored in the FIFO scaled to the narrowest (deepest) port
1085    // (Do not include data in FWFT stages)
1086    //Used to calculate PROG_FULL.
1087    wire [31:0] num_write_words_pf =
1088      num_wr_bits/(C_DIN_WIDTH/C_DEPTH_RATIO_RD);
1089
1090    /**************************
1091     * Read Data Count
1092     *************************/
1093
1094    /* ORIGINAL CODE - Removed 10/24/07 jeo
1095    //Amount of data stored in the FIFO scaled to read words
1096    // (Do not include data in FWFT stages)
1097    //Not used in the code.
1098    wire [31:0] num_read_words_dc = num_rd_bits/C_DOUT_WIDTH;
1099
1100    //Amount of data stored in the FIFO scaled to read words
1101    // (Include data in FWFT stages)
1102    //Not used in the code.
1103    wire [31:0] num_read_words_fwft_dc = (num_rd_bits/C_DOUT_WIDTH+2);
1104
1105    //Not used in the code.
1106    wire [31:0] num_read_words_dc_i =
1107      C_USE_FWFT_DATA_COUNT ? num_read_words_fwft_dc : num_read_words_dc;
1108
1109    //Not used in the code.
1110    wire [C_RD_DATA_COUNT_WIDTH-1:0] num_read_words_sized =
1111      num_read_words_dc_i[C_RD_PNTR_WIDTH-1 : C_RD_PNTR_WIDTH-C_RD_DATA_COUNT_WIDTH];
1112
1113    //Not used in the code.
1114    wire [C_RD_DATA_COUNT_WIDTH-1:0] num_read_words_sized_fwft =
1115      num_read_words_dc_i[C_RD_PNTR_WIDTH : C_RD_PNTR_WIDTH-C_RD_DATA_COUNT_WIDTH+1];
1116
1117    //Used to calculate ideal_rd_count (RD_DATA_COUNT)
1118    wire [C_RD_DATA_COUNT_WIDTH-1:0] num_read_words_sized_i =
1119      C_USE_FWFT_DATA_COUNT ? num_read_words_sized_fwft : num_read_words_sized;
1120    */
1121
1122    reg [31:0] num_read_words_dc;
1123    reg [C_RD_DATA_COUNT_WIDTH-1:0] num_read_words_sized_i;
1124
1125    always @(num_rd_bits) begin
1126      if (C_USE_FWFT_DATA_COUNT) begin
1127
1128         //If using extra logic for FWFT Data Counts,
1129         // then scale FIFO contents to read domain,
1130         // and add two read words for FWFT stages
1131         //This value is only a temporary value and not used in the code.
1132         num_read_words_dc = (num_rd_bits/C_DOUT_WIDTH+2);
1133
1134         //Trim the read words for use with RD_DATA_COUNT
1135         num_read_words_sized_i =
1136           num_read_words_dc[C_RD_PNTR_WIDTH : C_RD_PNTR_WIDTH-C_RD_DATA_COUNT_WIDTH+1];
1137
1138      end else begin
1139
1140         //If not using extra logic for FWFT Data Counts,
1141         // then scale FIFO contents to read domain.
1142         //This value is only a temporary value and not used in the code.
1143         num_read_words_dc = num_rd_bits/C_DOUT_WIDTH;
1144
1145         //Trim the read words for use with RD_DATA_COUNT
1146         num_read_words_sized_i =
1147           num_read_words_dc[C_RD_PNTR_WIDTH-1 : C_RD_PNTR_WIDTH-C_RD_DATA_COUNT_WIDTH];
1148
1149      end //if (C_USE_FWFT_DATA_COUNT)
1150    end //always
1151
1152
1153
1154
1155
1156
1157
1158
1159    /**************************
1160     * Write Data Count
1161     *************************/
1162    /* ORIGINAL CODE - Removed 10/24/07 jeo
1163
1164    //Calculate the Data Count value for the number of write words, when not
1165    // using First-Word Fall-Through with extra logic for Data Counts. This
1166    // calculates only the number of words in the internal FIFO.
1167    //The expression (((A-1)/B))+1 divides A/B, but takes the
1168    // ceiling of the result.
1169    //When num_wr_bits==0, set the result manually to prevent division errors.
1170    wire [31:0]  num_write_words_dc =
1171      (num_wr_bits==0) ? 0 : ((num_wr_bits-1)/C_DIN_WIDTH) + 1;
1172
1173    //Calculate the Data Count value for the number of write words, when using
1174    // First-Word Fall-Through with extra logic for Data Counts. This takes into
1175    // consideration the number of words that are expected to be stored in the
1176    // FWFT register stages (it always assumes they are filled).
1177    //The expression (((A-1)/B))+1 divides A/B, but takes the
1178    // ceiling of the result.
1179    //When num_wr_bits==0, set the result manually to prevent division errors.
1180    //EXTRA_WORDS_DC is the number of words added to write_words due to FWFT.
1181    wire [31:0] num_write_words_fwft_dc =
1182      (num_wr_bits==0) ? EXTRA_WORDS_DC :  (((num_wr_bits-1)/C_DIN_WIDTH) + 1) + EXTRA_WORDS_DC ;
1183
1184    wire [31:0] num_write_words_dc_i =
1185      C_USE_FWFT_DATA_COUNT ? num_write_words_fwft_dc : num_write_words_dc;
1186
1187
1188
1189    wire [C_WR_DATA_COUNT_WIDTH-1:0] num_write_words_sized =
1190      num_write_words_dc_i[C_WR_PNTR_WIDTH-1 : C_WR_PNTR_WIDTH-C_WR_DATA_COUNT_WIDTH];
1191
1192    wire [C_WR_DATA_COUNT_WIDTH-1:0] num_write_words_sized_fwft =
1193      num_write_words_dc_i[C_WR_PNTR_WIDTH : C_WR_PNTR_WIDTH-C_WR_DATA_COUNT_WIDTH+1];
1194
1195        wire [C_WR_DATA_COUNT_WIDTH-1:0] num_write_words_sized_i = C_USE_FWFT_DATA_COUNT?
1196                                 num_write_words_sized_fwft:num_write_words_sized;
1197
1198    */
1199
1200    reg [31:0] num_write_words_dc;
1201    reg [C_WR_DATA_COUNT_WIDTH-1:0] num_write_words_sized_i;
1202
1203    always @(num_wr_bits) begin
1204      if (C_USE_FWFT_DATA_COUNT) begin
1205
1206         //Calculate the Data Count value for the number of write words,
1207         // when using First-Word Fall-Through with extra logic for Data
1208         // Counts. This takes into consideration the number of words that
1209         // are expected to be stored in the FWFT register stages (it always
1210         // assumes they are filled).
1211         //This value is scaled to the Write Domain.
1212         //The expression (((A-1)/B))+1 divides A/B, but takes the
1213         // ceiling of the result.
1214         //When num_wr_bits==0, set the result manually to prevent
1215         // division errors.
1216         //EXTRA_WORDS_DC is the number of words added to write_words
1217         // due to FWFT.
1218         //This value is only a temporary value and not used in the code.
1219         num_write_words_dc = (num_wr_bits==0) ? EXTRA_WORDS_DC :  (((num_wr_bits-1)/C_DIN_WIDTH)+1) + EXTRA_WORDS_DC ;
1220
1221         //Trim the write words for use with WR_DATA_COUNT
1222         num_write_words_sized_i =
1223           num_write_words_dc[C_WR_PNTR_WIDTH : C_WR_PNTR_WIDTH-C_WR_DATA_COUNT_WIDTH+1];
1224
1225      end else begin
1226
1227         //Calculate the Data Count value for the number of write words, when NOT
1228         // using First-Word Fall-Through with extra logic for Data Counts. This
1229         // calculates only the number of words in the internal FIFO.
1230         //The expression (((A-1)/B))+1 divides A/B, but takes the
1231         // ceiling of the result.
1232         //This value is scaled to the Write Domain.
1233         //When num_wr_bits==0, set the result manually to prevent
1234         // division errors.
1235         //This value is only a temporary value and not used in the code.
1236         num_write_words_dc = (num_wr_bits==0) ? 0 : ((num_wr_bits-1)/C_DIN_WIDTH)+1;
1237
1238         //Trim the read words for use with RD_DATA_COUNT
1239         num_write_words_sized_i =
1240           num_write_words_dc[C_WR_PNTR_WIDTH-1 : C_WR_PNTR_WIDTH-C_WR_DATA_COUNT_WIDTH];
1241
1242      end //if (C_USE_FWFT_DATA_COUNT)
1243    end //always
1244
1245
1246
1247    /***************************************************************************
1248     * Internal registers and wires
1249     **************************************************************************/
1250
1251    //Temporary signals used for calculating the model's outputs. These
1252    //are only used in the assign statements immediately following wire,
1253    //parameter, and function declarations.
1254    wire [C_DOUT_WIDTH-1:0] ideal_dout_out;
1255    wire valid_i;
1256    wire valid_out;
1257    wire underflow_i;
1258
1259    //Ideal FIFO signals. These are the raw output of the behavioral model,
1260    //which behaves like an ideal FIFO.
1261    reg [C_DOUT_WIDTH-1:0] ideal_dout;
1262    reg [C_DOUT_WIDTH-1:0]  ideal_dout_d1;
1263    reg                     ideal_wr_ack;
1264    reg                     ideal_valid;
1265    reg                     ideal_overflow;
1266    reg                     ideal_underflow;
1267    reg                     ideal_full;
1268    reg                     ideal_empty;
1269    reg                     ideal_almost_full;
1270    reg                     ideal_almost_empty;
1271    reg                     ideal_prog_full;
1272    reg                     ideal_prog_empty;
1273    reg [C_WR_DATA_COUNT_WIDTH-1 : 0] ideal_wr_count;
1274    reg [C_RD_DATA_COUNT_WIDTH-1 : 0] ideal_rd_count;
1275
1276    //Assorted reg values for delayed versions of signals
1277    reg         valid_d1;
1278    reg         prog_full_d;
1279    reg         prog_empty_d;
1280
1281    //Internal reset signals
1282    reg         rd_rst_asreg    =0;
1283    reg         rd_rst_asreg_d1 =0;
1284    reg         rd_rst_asreg_d2 =0;
1285    reg         rd_rst_reg      =0;
1286    reg         rd_rst_d1       =0;
1287    reg         wr_rst_asreg    =0;
1288    reg         wr_rst_asreg_d1 =0;
1289    reg         wr_rst_asreg_d2 =0;
1290    reg         wr_rst_reg      =0;
1291    reg         wr_rst_d1       =0;
1292
1293    wire        rd_rst_comb;
1294    wire        rd_rst_i;
1295    wire        wr_rst_comb;
1296    wire        wr_rst_i;
1297
1298
1299    //user specified value for reseting the size of the fifo
1300    reg [C_DOUT_WIDTH-1:0]            dout_reset_val;
1301
1302    //temporary registers for WR_RESPONSE_LATENCY feature
1303
1304    integer                           tmp_wr_listsize;
1305    integer                           tmp_rd_listsize;
1306
1307    //Signal for registered version of prog full and empty
1308
1309    //Threshold values for Programmable Flags
1310    integer                           prog_empty_actual_thresh_assert;
1311    integer                           prog_empty_actual_thresh_negate;
1312    integer                           prog_full_actual_thresh_assert;
1313    integer                           prog_full_actual_thresh_negate;
1314
1315
1316   /****************************************************************************
1317    * Function Declarations
1318    ***************************************************************************/
1319
1320   /**************************************************************************
1321    * write_fifo
1322    *   This task writes a word to the FIFO memory and updates the
1323    * write pointer.
1324    *   FIFO size is relative to write domain.
1325   ***************************************************************************/
1326   task write_fifo;
1327     begin
1328       memory[wr_ptr]     <= DIN;
1329       // (Works opposite to core: wr_ptr is a DOWN counter)
1330       if (wr_ptr == 0) begin
1331         wr_ptr          <= C_WR_DEPTH - 1;
1332       end else begin
1333         wr_ptr          <= wr_ptr - 1;
1334       end
1335     end
1336   endtask // write_fifo
1337
1338   /**************************************************************************
1339    * read_fifo
1340    *   This task reads a word from the FIFO memory and updates the read
1341    * pointer. It's output is the ideal_dout bus.
1342    *   FIFO size is relative to write domain.
1343    ***************************************************************************/
1344   task read_fifo;
1345     integer i;
1346     reg [C_DOUT_WIDTH-1:0] tmp_dout;
1347     reg [C_DIN_WIDTH-1:0]  memory_read;
1348     reg [31:0]             tmp_rd_ptr;
1349     reg [31:0]             rd_ptr_high;
1350     reg [31:0]             rd_ptr_low;
1351     begin
1352       // output is wider than input
1353       if (reads_per_write == 0) begin
1354         tmp_dout = 0;
1355         tmp_rd_ptr = (rd_ptr << log2_writes_per_read)+(writes_per_read-1);
1356         for (i = writes_per_read - 1; i >= 0; i = i - 1) begin
1357           tmp_dout = tmp_dout << C_DIN_WIDTH;
1358           tmp_dout = tmp_dout | memory[tmp_rd_ptr];
1359
1360           // (Works opposite to core: rd_ptr is a DOWN counter)
1361           if (tmp_rd_ptr == 0) begin
1362             tmp_rd_ptr = C_WR_DEPTH - 1;
1363           end else begin
1364             tmp_rd_ptr = tmp_rd_ptr - 1;
1365           end
1366         end
1367
1368       // output is symmetric
1369       end else if (reads_per_write == 1) begin
1370         tmp_dout = memory[rd_ptr];
1371
1372       // input is wider than output
1373       end else begin
1374         rd_ptr_high = rd_ptr >> log2_reads_per_write;
1375         rd_ptr_low  = rd_ptr & (reads_per_write - 1);
1376         memory_read = memory[rd_ptr_high];
1377         tmp_dout    = memory_read >> (rd_ptr_low*C_DOUT_WIDTH);
1378       end
1379       ideal_dout <= tmp_dout;
1380
1381       // (Works opposite to core: rd_ptr is a DOWN counter)
1382       if (rd_ptr == 0) begin
1383         rd_ptr <= C_RD_DEPTH - 1;
1384       end else begin
1385         rd_ptr <= rd_ptr - 1;
1386       end
1387     end
1388   endtask
1389
1390   /**************************************************************************
1391   * log2_val
1392   *   Returns the 'log2' value for the input value for the supported ratios
1393   ***************************************************************************/
1394   function [31:0] log2_val;
1395     input [31:0] binary_val;
1396
1397     begin
1398       if (binary_val == 8) begin
1399         log2_val = 3;
1400       end else if (binary_val == 4) begin
1401         log2_val = 2;
1402       end else begin
1403         log2_val = 1;
1404       end
1405     end
1406   endfunction
1407
1408   /***********************************************************************
1409   * hexstr_conv
1410   *   Converts a string of type hex to a binary value (for C_DOUT_RST_VAL)
1411   ***********************************************************************/
1412   function [C_DOUT_WIDTH-1:0] hexstr_conv;
1413     input [(C_DOUT_WIDTH*8)-1:0] def_data;
1414
1415     integer index,i,j;
1416     reg [3:0] bin;
1417
1418     begin
1419       index = 0;
1420       hexstr_conv = 'b0;
1421       for( i=C_DOUT_WIDTH-1; i>=0; i=i-1 )
1422       begin
1423         case (def_data[7:0])
1424           8'b00000000 :
1425           begin
1426             bin = 4'b0000;
1427             i = -1;
1428           end
1429           8'b00110000 : bin = 4'b0000;
1430           8'b00110001 : bin = 4'b0001;
1431           8'b00110010 : bin = 4'b0010;
1432           8'b00110011 : bin = 4'b0011;
1433           8'b00110100 : bin = 4'b0100;
1434           8'b00110101 : bin = 4'b0101;
1435           8'b00110110 : bin = 4'b0110;
1436           8'b00110111 : bin = 4'b0111;
1437           8'b00111000 : bin = 4'b1000;
1438           8'b00111001 : bin = 4'b1001;
1439           8'b01000001 : bin = 4'b1010;
1440           8'b01000010 : bin = 4'b1011;
1441           8'b01000011 : bin = 4'b1100;
1442           8'b01000100 : bin = 4'b1101;
1443           8'b01000101 : bin = 4'b1110;
1444           8'b01000110 : bin = 4'b1111;
1445           8'b01100001 : bin = 4'b1010;
1446           8'b01100010 : bin = 4'b1011;
1447           8'b01100011 : bin = 4'b1100;
1448           8'b01100100 : bin = 4'b1101;
1449           8'b01100101 : bin = 4'b1110;
1450           8'b01100110 : bin = 4'b1111;
1451           default :
1452           begin
1453             bin = 4'bx;
1454           end
1455         endcase
1456         for( j=0; j<4; j=j+1)
1457         begin
1458           if ((index*4)+j < C_DOUT_WIDTH)
1459           begin
1460             hexstr_conv[(index*4)+j] = bin[j];
1461           end
1462         end
1463         index = index + 1;
1464         def_data = def_data >> 8;
1465       end
1466     end
1467   endfunction
1468
1469   /*************************************************************************
1470   * Initialize Signals for clean power-on simulation
1471   *************************************************************************/
1472    initial begin
1473       num_wr_bits        = 0;
1474       num_rd_bits        = 0;
1475       next_num_wr_bits   = 0;
1476       next_num_rd_bits   = 0;
1477       rd_ptr             = C_RD_DEPTH - 1;
1478       wr_ptr             = C_WR_DEPTH - 1;
1479       rd_ptr_wrclk       = rd_ptr;
1480       wr_ptr_rdclk       = wr_ptr;
1481       dout_reset_val     = hexstr_conv(C_DOUT_RST_VAL);
1482       ideal_dout         = dout_reset_val;
1483       ideal_dout_d1      = 0 ;
1484       ideal_wr_ack       = 1'b0;
1485       ideal_valid        = 1'b0;
1486       valid_d1           = 1'b0;
1487       ideal_overflow     = 1'b0;
1488       ideal_underflow    = 1'b0;
1489       ideal_full         = 1'b0;
1490       ideal_empty        = 1'b1;
1491       ideal_almost_full  = 1'b0;
1492       ideal_almost_empty = 1'b1;
1493       ideal_wr_count     = 0;
1494       ideal_rd_count     = 0;
1495       ideal_prog_full    = 1'b0;
1496       ideal_prog_empty   = 1'b1;
1497       prog_full_d        = 1'b0;
1498       prog_empty_d       = 1'b1;
1499     end
1500
1501
1502   /*************************************************************************
1503    * Connect the module inputs and outputs to the internal signals of the
1504    * behavioral model.
1505    *************************************************************************/
1506    //Inputs
1507    /*
1508     wire [C_DIN_WIDTH-1:0] DIN;
1509    wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH;
1510    wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_ASSERT;
1511    wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_NEGATE;
1512    wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH;
1513    wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_ASSERT;
1514    wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_NEGATE;
1515    wire RD_CLK;
1516    wire RD_EN;
1517    wire RST;
1518    wire WR_CLK;
1519    wire WR_EN;
1520     */
1521
1522    //Outputs
1523    assign ALMOST_EMPTY = ideal_almost_empty;
1524    assign ALMOST_FULL  = ideal_almost_full;
1525
1526    //Dout may change behavior based on latency
1527    assign ideal_dout_out[C_DOUT_WIDTH-1:0] = (C_PRELOAD_LATENCY==2 &&
1528                           (C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1))?
1529                          ideal_dout_d1: ideal_dout;
1530    assign DOUT[C_DOUT_WIDTH-1:0] = ideal_dout_out;
1531
1532    assign EMPTY = ideal_empty;
1533    assign FULL  = ideal_full;
1534
1535    //Overflow may be active-low
1536    assign OVERFLOW = ideal_overflow ? !C_OVERFLOW_LOW : C_OVERFLOW_LOW;
1537
1538    assign PROG_EMPTY = ideal_prog_empty;
1539    assign PROG_FULL  = ideal_prog_full;
1540
1541    //Valid may change behavior based on latency or active-low
1542    assign valid_i   = (C_PRELOAD_LATENCY==0) ? (RD_EN & ~EMPTY) : ideal_valid;
1543    assign valid_out = (C_PRELOAD_LATENCY==2 &&
1544                        (C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1))?
1545                        valid_d1: valid_i;
1546    assign VALID     = valid_out ? !C_VALID_LOW : C_VALID_LOW;
1547
1548    assign RD_DATA_COUNT[C_RD_DATA_COUNT_WIDTH-1:0] = ideal_rd_count;
1549
1550    //Underflow may change behavior based on latency or active-low
1551    assign underflow_i = (C_PRELOAD_LATENCY==0) ? (RD_EN & EMPTY) : ideal_underflow;
1552    assign UNDERFLOW   = underflow_i ? !C_UNDERFLOW_LOW : C_UNDERFLOW_LOW;
1553
1554    //Write acknowledge may be active low
1555    assign WR_ACK = ideal_wr_ack ? !C_WR_ACK_LOW : C_WR_ACK_LOW;
1556
1557    assign WR_DATA_COUNT[C_WR_DATA_COUNT_WIDTH-1:0] = ideal_wr_count;
1558
1559
1560   /**************************************************************************
1561   * Internal reset logic
1562   **************************************************************************/
1563   assign wr_rst_comb      = !wr_rst_asreg_d2 && wr_rst_asreg;
1564   assign rd_rst_comb      = !rd_rst_asreg_d2 && rd_rst_asreg;
1565   assign wr_rst_i         = C_HAS_RST ? wr_rst_reg : 0;
1566   assign rd_rst_i         = C_HAS_RST ? rd_rst_reg : 0;
1567
1568
1569   always @(posedge WR_CLK or posedge RST) begin
1570     if (RST == 1'b1) begin
1571       wr_rst_asreg <= 1'b1;
1572     end else begin
1573       if (wr_rst_asreg_d1 == 1'b1) begin
1574         wr_rst_asreg <= 1'b0;
1575       end else begin
1576         wr_rst_asreg <= wr_rst_asreg;
1577       end
1578     end
1579   end
1580
1581   always @(posedge WR_CLK) begin
1582     wr_rst_asreg_d1 <= wr_rst_asreg;
1583     wr_rst_asreg_d2 <= wr_rst_asreg_d1;
1584   end
1585
1586   always @(posedge WR_CLK or posedge wr_rst_comb) begin
1587     if (wr_rst_comb == 1'b1) begin
1588       wr_rst_reg <= 1'b1;
1589     end else begin
1590       wr_rst_reg <= 1'b0;
1591     end
1592   end
1593
1594   always @(posedge WR_CLK or posedge wr_rst_i) begin
1595     if (wr_rst_i == 1'b1) begin
1596       wr_rst_d1 <= 1'b1;
1597     end else begin
1598       wr_rst_d1 <= wr_rst_i;
1599     end
1600   end
1601   always @(posedge RD_CLK or posedge RST) begin
1602     if (RST == 1'b1) begin
1603       rd_rst_asreg <= 1'b1;
1604     end else begin
1605       if (rd_rst_asreg_d1 == 1'b1) begin
1606         rd_rst_asreg <= 1'b0;
1607       end else begin
1608         rd_rst_asreg <= rd_rst_asreg;
1609       end
1610     end
1611   end
1612
1613   always @(posedge RD_CLK) begin
1614     rd_rst_asreg_d1 <= rd_rst_asreg;
1615     rd_rst_asreg_d2 <= rd_rst_asreg_d1;
1616   end
1617
1618   always @(posedge RD_CLK or posedge rd_rst_comb) begin
1619     if (rd_rst_comb == 1'b1) begin
1620       rd_rst_reg <= 1'b1;
1621     end else begin
1622       rd_rst_reg <= 1'b0;
1623     end
1624   end
1625
1626   /**************************************************************************
1627   * Assorted registers for delayed versions of signals
1628   **************************************************************************/
1629   //Capture delayed version of valid
1630   always @(posedge RD_CLK or posedge rd_rst_i) begin
1631     if (rd_rst_i == 1'b1) begin
1632       valid_d1 <= 1'b0;
1633     end else begin
1634       valid_d1 <= valid_i;
1635     end
1636   end
1637
1638   //Capture delayed version of dout
1639   always @(posedge RD_CLK or posedge rd_rst_i) begin
1640     if (rd_rst_i == 1'b1 && C_USE_DOUT_RST == 1) begin
1641       ideal_dout_d1 <= dout_reset_val;
1642     end else begin
1643       ideal_dout_d1 <= ideal_dout;
1644     end
1645   end
1646
1647    /**************************************************************************
1648     * Overflow and Underflow Flag calculation
1649     *  (handled separately because they don't support rst)
1650     **************************************************************************/
1651    always @(posedge WR_CLK) begin
1652      ideal_overflow    <= WR_EN & ideal_full;
1653    end
1654
1655    always @(posedge RD_CLK) begin
1656      ideal_underflow    <= ideal_empty & RD_EN;
1657    end
1658
1659    /**************************************************************************
1660    * Write Domain Logic
1661    **************************************************************************/
1662    always @(posedge WR_CLK or posedge wr_rst_i) begin : gen_fifo_w
1663
1664      /****** Reset fifo (case 1)***************************************/
1665      if (wr_rst_i == 1'b1) begin
1666        num_wr_bits       <= 0;
1667        next_num_wr_bits  <= 0;
1668        wr_ptr            <= C_WR_DEPTH - 1;
1669        rd_ptr_wrclk      <= C_RD_DEPTH - 1;
1670        ideal_wr_ack      <= 0;
1671        ideal_full        <= C_FULL_FLAGS_RST_VAL;
1672        ideal_almost_full <= C_FULL_FLAGS_RST_VAL;
1673        ideal_wr_count    <= 0;
1674
1675        ideal_prog_full   <= C_FULL_FLAGS_RST_VAL;
1676        prog_full_d       <= C_FULL_FLAGS_RST_VAL;
1677
1678      end else begin //wr_rst_i==0
1679
1680        //Determine the current number of words in the FIFO
1681        tmp_wr_listsize = (C_DEPTH_RATIO_RD > 1) ? num_wr_bits/C_DOUT_WIDTH :
1682                          num_wr_bits/C_DIN_WIDTH;
1683        rd_ptr_wrclk_next = rd_ptr;
1684        if (rd_ptr_wrclk < rd_ptr_wrclk_next) begin
1685          next_num_wr_bits = num_wr_bits -
1686                             C_DOUT_WIDTH*(rd_ptr_wrclk + C_RD_DEPTH
1687                                           - rd_ptr_wrclk_next);
1688        end else begin
1689          next_num_wr_bits = num_wr_bits -
1690                             C_DOUT_WIDTH*(rd_ptr_wrclk - rd_ptr_wrclk_next);
1691        end
1692
1693        //If this is a write, handle the write by adding the value
1694        // to the linked list, and updating all outputs appropriately
1695        if (WR_EN == 1'b1) begin
1696          if (ideal_full == 1'b1) begin
1697
1698            //If the FIFO is full, do NOT perform the write,
1699            // update flags accordingly
1700            if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD
1701              >= C_FIFO_WR_DEPTH) begin
1702              //write unsuccessful - do not change contents
1703
1704              //Do not acknowledge the write
1705              ideal_wr_ack      <= 0;
1706              //Reminder that FIFO is still full
1707              ideal_full        <= 1'b1;
1708              ideal_almost_full <= 1'b1;
1709
1710              ideal_wr_count    <= num_write_words_sized_i;
1711
1712            //If the FIFO is one from full, but reporting full
1713            end else
1714              if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD ==
1715                 C_FIFO_WR_DEPTH-1) begin
1716              //No change to FIFO
1717
1718              //Write not successful
1719              ideal_wr_ack      <= 0;
1720              //With DEPTH-1 words in the FIFO, it is almost_full
1721              ideal_full        <= 1'b0;
1722              ideal_almost_full <= 1'b1;
1723
1724              ideal_wr_count    <= num_write_words_sized_i;
1725
1726
1727            //If the FIFO is completely empty, but it is
1728            // reporting FULL for some reason (like reset)
1729            end else
1730              if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD <=
1731                 C_FIFO_WR_DEPTH-2) begin
1732              //No change to FIFO
1733
1734              //Write not successful
1735              ideal_wr_ack      <= 0;
1736              //FIFO is really not close to full, so change flag status.
1737              ideal_full        <= 1'b0;
1738              ideal_almost_full <= 1'b0;
1739
1740              ideal_wr_count    <= num_write_words_sized_i;
1741            end //(tmp_wr_listsize == 0)
1742
1743          end else begin
1744
1745            //If the FIFO is full, do NOT perform the write,
1746            // update flags accordingly
1747            if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD >=
1748               C_FIFO_WR_DEPTH) begin
1749              //write unsuccessful - do not change contents
1750
1751              //Do not acknowledge the write
1752              ideal_wr_ack       <= 0;
1753              //Reminder that FIFO is still full
1754              ideal_full         <= 1'b1;
1755              ideal_almost_full  <= 1'b1;
1756
1757              ideal_wr_count     <= num_write_words_sized_i;
1758
1759            //If the FIFO is one from full
1760            end else
1761              if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD ==
1762                 C_FIFO_WR_DEPTH-1) begin
1763              //Add value on DIN port to FIFO
1764              write_fifo;
1765              next_num_wr_bits = next_num_wr_bits + C_DIN_WIDTH;
1766
1767              //Write successful, so issue acknowledge
1768              // and no error
1769              ideal_wr_ack      <= 1;
1770              //This write is CAUSING the FIFO to go full
1771              ideal_full        <= 1'b1;
1772              ideal_almost_full <= 1'b1;
1773
1774              ideal_wr_count    <= num_write_words_sized_i;
1775
1776            //If the FIFO is 2 from full
1777            end else
1778              if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD ==
1779                 C_FIFO_WR_DEPTH-2) begin
1780              //Add value on DIN port to FIFO
1781              write_fifo;
1782              next_num_wr_bits =  next_num_wr_bits + C_DIN_WIDTH;
1783              //Write successful, so issue acknowledge
1784              // and no error
1785              ideal_wr_ack      <= 1;
1786              //Still 2 from full
1787              ideal_full        <= 1'b0;
1788              //2 from full, and writing, so set almost_full
1789              ideal_almost_full <= 1'b1;
1790
1791              ideal_wr_count    <= num_write_words_sized_i;
1792
1793            //If the FIFO is not close to being full
1794            end else
1795              if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD <
1796                 C_FIFO_WR_DEPTH-2) begin
1797              //Add value on DIN port to FIFO
1798              write_fifo;
1799              next_num_wr_bits  = next_num_wr_bits + C_DIN_WIDTH;
1800              //Write successful, so issue acknowledge
1801              // and no error
1802              ideal_wr_ack      <= 1;
1803              //Not even close to full.
1804              ideal_full        <= 1'b0;
1805              ideal_almost_full <= 1'b0;
1806
1807              ideal_wr_count    <= num_write_words_sized_i;
1808
1809            end
1810
1811          end
1812
1813        end else begin //(WR_EN == 1'b1)
1814
1815          //If user did not attempt a write, then do not
1816          // give ack or err
1817          ideal_wr_ack   <= 0;
1818
1819          //Implied statements:
1820          //ideal_empty <= ideal_empty;
1821          //ideal_almost_empty <= ideal_almost_empty;
1822
1823          //Check for full
1824          if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD >= C_FIFO_WR_DEPTH)
1825            ideal_full <= 1'b1;
1826          else
1827            ideal_full <= 1'b0;
1828
1829          //Check for almost_full
1830          if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD >= C_FIFO_WR_DEPTH-1)
1831            ideal_almost_full  <= 1'b1;
1832          else
1833            ideal_almost_full  <= 1'b0;
1834
1835          ideal_wr_count <= num_write_words_sized_i;
1836        end
1837
1838        /*********************************************************
1839         * Programmable FULL flags
1840         *********************************************************/
1841        //Single Programmable Full Constant Threshold
1842        if (C_PROG_FULL_TYPE==1) begin
1843          if (C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0) begin
1844            prog_full_actual_thresh_assert = C_PROG_FULL_THRESH_ASSERT_VAL-EXTRA_WORDS;
1845            prog_full_actual_thresh_negate = C_PROG_FULL_THRESH_ASSERT_VAL-EXTRA_WORDS;
1846          end else begin
1847            prog_full_actual_thresh_assert = C_PROG_FULL_THRESH_ASSERT_VAL;
1848            prog_full_actual_thresh_negate = C_PROG_FULL_THRESH_ASSERT_VAL;
1849          end
1850
1851        //Two Programmable Full Constant Thresholds
1852        end else if (C_PROG_FULL_TYPE==2) begin
1853          if (C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0) begin
1854            prog_full_actual_thresh_assert = C_PROG_FULL_THRESH_ASSERT_VAL-EXTRA_WORDS;
1855            prog_full_actual_thresh_negate = C_PROG_FULL_THRESH_NEGATE_VAL-EXTRA_WORDS;
1856          end else begin
1857            prog_full_actual_thresh_assert = C_PROG_FULL_THRESH_ASSERT_VAL;
1858            prog_full_actual_thresh_negate = C_PROG_FULL_THRESH_NEGATE_VAL;
1859          end
1860
1861        //Single Programmable Full Threshold Input
1862        end else if (C_PROG_FULL_TYPE==3) begin
1863          if (C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0) begin
1864            prog_full_actual_thresh_assert = PROG_FULL_THRESH-EXTRA_WORDS;
1865            prog_full_actual_thresh_negate = PROG_FULL_THRESH-EXTRA_WORDS;
1866          end else begin
1867            prog_full_actual_thresh_assert = PROG_FULL_THRESH;
1868            prog_full_actual_thresh_negate = PROG_FULL_THRESH;
1869          end
1870
1871        //Two Programmable Full Threshold Inputs
1872        end else if (C_PROG_FULL_TYPE==4) begin
1873          if (C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0) begin
1874            prog_full_actual_thresh_assert = PROG_FULL_THRESH_ASSERT-EXTRA_WORDS;
1875            prog_full_actual_thresh_negate = PROG_FULL_THRESH_NEGATE-EXTRA_WORDS;
1876          end else begin
1877            prog_full_actual_thresh_assert = PROG_FULL_THRESH_ASSERT;
1878            prog_full_actual_thresh_negate = PROG_FULL_THRESH_NEGATE;
1879          end
1880        end //C_PROG_FULL_TYPE
1881
1882        if (num_write_words_pf==0) begin
1883           prog_full_d <= 1'b0;
1884        end else begin
1885          if (((1+(num_write_words_pf-1)/C_DEPTH_RATIO_RD)
1886               == prog_full_actual_thresh_assert-1) && WR_EN) begin
1887             prog_full_d <= 1'b1;
1888          end else if ((1+(num_write_words_pf-1)/C_DEPTH_RATIO_RD)
1889                       >= prog_full_actual_thresh_assert) begin
1890             prog_full_d <= 1'b1;
1891          end else if ((1+(num_write_words_pf-1)/C_DEPTH_RATIO_RD)
1892                       < prog_full_actual_thresh_negate) begin
1893             prog_full_d <= 1'b0;
1894          end
1895        end
1896
1897        if (wr_rst_d1==1 && wr_rst_i==0) begin
1898          ideal_prog_full   <= 0;
1899        end else begin
1900          ideal_prog_full   <= prog_full_d;
1901        end
1902        num_wr_bits       <= next_num_wr_bits;
1903        rd_ptr_wrclk      <= rd_ptr;
1904
1905      end //wr_rst_i==0
1906    end // write always
1907
1908
1909    /**************************************************************************
1910    * Read Domain Logic
1911    **************************************************************************/
1912    always @(posedge RD_CLK or posedge rd_rst_i) begin : gen_fifo_r
1913
1914      /****** Reset fifo (case 1)***************************************/
1915      if (rd_rst_i) begin
1916        num_rd_bits        <= 0;
1917        next_num_rd_bits   <= 0;
1918        rd_ptr             <= C_RD_DEPTH -1;
1919        wr_ptr_rdclk       <= C_WR_DEPTH -1;
1920        if (C_USE_DOUT_RST == 1) begin
1921        ideal_dout         <= dout_reset_val;
1922        end else begin
1923        ideal_dout         <= ideal_dout;
1924        end
1925        ideal_valid        <= 1'b0;
1926        ideal_empty        <= 1'b1;
1927        ideal_almost_empty <= 1'b1;
1928        ideal_rd_count     <= 0;
1929
1930        ideal_prog_empty   <= 1'b1;
1931        prog_empty_d       <= 1;
1932
1933
1934      end else begin //rd_rst_i==0
1935
1936        //Determine the current number of words in the FIFO
1937        tmp_rd_listsize = (C_DEPTH_RATIO_WR > 1) ? num_rd_bits/C_DIN_WIDTH :
1938                          num_rd_bits/C_DOUT_WIDTH;
1939        wr_ptr_rdclk_next = wr_ptr;
1940
1941        if (wr_ptr_rdclk < wr_ptr_rdclk_next) begin
1942          next_num_rd_bits = num_rd_bits +
1943                             C_DIN_WIDTH*(wr_ptr_rdclk +C_WR_DEPTH
1944                                          - wr_ptr_rdclk_next);
1945        end else begin
1946          next_num_rd_bits = num_rd_bits +
1947                              C_DIN_WIDTH*(wr_ptr_rdclk - wr_ptr_rdclk_next);
1948        end
1949
1950        /*****************************************************************/
1951        // Read Operation - Read Latency 1
1952        /*****************************************************************/
1953        if (C_PRELOAD_LATENCY==1 || C_PRELOAD_LATENCY==2) begin
1954
1955          if (RD_EN == 1'b1) begin
1956
1957            if (ideal_empty == 1'b1) begin
1958
1959              //If the FIFO is completely empty, and is reporting empty
1960              if (tmp_rd_listsize/C_DEPTH_RATIO_WR <= 0)
1961                begin
1962                  //Do not change the contents of the FIFO
1963
1964                  //Do not acknowledge the read from empty FIFO
1965                  ideal_valid        <= 1'b0;
1966                  //Reminder that FIFO is still empty
1967                  ideal_empty        <= 1'b1;
1968                  ideal_almost_empty <= 1'b1;
1969
1970                  ideal_rd_count     <= num_read_words_sized_i;
1971                end // if (tmp_rd_listsize <= 0)
1972
1973              //If the FIFO is one from empty, but it is reporting empty
1974              else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 1)
1975                begin
1976                  //Do not change the contents of the FIFO
1977
1978                  //Do not acknowledge the read from empty FIFO
1979                  ideal_valid        <= 1'b0;
1980                  //Note that FIFO is no longer empty, but is almost empty (has one word left)
1981                  ideal_empty        <= 1'b0;
1982                  ideal_almost_empty <= 1'b1;
1983
1984                  ideal_rd_count     <= num_read_words_sized_i;
1985
1986                end // if (tmp_rd_listsize == 1)
1987
1988              //If the FIFO is two from empty, and is reporting empty
1989              else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 2)
1990                begin
1991                  //Do not change the contents of the FIFO
1992
1993                  //Do not acknowledge the read from empty FIFO
1994                  ideal_valid        <= 1'b0;
1995                  //Fifo has two words, so is neither empty or almost empty
1996                  ideal_empty        <= 1'b0;
1997                  ideal_almost_empty <= 1'b0;
1998
1999                  ideal_rd_count     <= num_read_words_sized_i;
2000
2001                end // if (tmp_rd_listsize == 2)
2002
2003              //If the FIFO is not close to empty, but is reporting that it is
2004              // Treat the FIFO as empty this time, but unset EMPTY flags.
2005              if ((tmp_rd_listsize/C_DEPTH_RATIO_WR > 2) && (tmp_rd_listsize/C_DEPTH_RATIO_WR<C_FIFO_RD_DEPTH))
2006                begin
2007                  //Do not change the contents of the FIFO
2008
2009                  //Do not acknowledge the read from empty FIFO
2010                  ideal_valid <= 1'b0;
2011                  //Note that the FIFO is No Longer Empty or Almost Empty
2012                  ideal_empty  <= 1'b0;
2013                  ideal_almost_empty <= 1'b0;
2014
2015                  ideal_rd_count <= num_read_words_sized_i;
2016
2017                end // if ((tmp_rd_listsize > 2) && (tmp_rd_listsize<=C_FIFO_RD_DEPTH-1))
2018              end // else: if(ideal_empty == 1'b1)
2019
2020            else //if (ideal_empty == 1'b0)
2021              begin
2022
2023                //If the FIFO is completely full, and we are successfully reading from it
2024                if (tmp_rd_listsize/C_DEPTH_RATIO_WR >= C_FIFO_RD_DEPTH)
2025                  begin
2026                    //Read the value from the FIFO
2027                    read_fifo;
2028                    next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH;
2029
2030                    //Acknowledge the read from the FIFO, no error
2031                    ideal_valid        <= 1'b1;
2032                    //Not close to empty
2033                    ideal_empty        <= 1'b0;
2034                    ideal_almost_empty <= 1'b0;
2035
2036                    ideal_rd_count     <= num_read_words_sized_i;
2037
2038                  end // if (tmp_rd_listsize == C_FIFO_RD_DEPTH)
2039
2040                //If the FIFO is not close to being empty
2041                else if ((tmp_rd_listsize/C_DEPTH_RATIO_WR > 2) && (tmp_rd_listsize/C_DEPTH_RATIO_WR<=C_FIFO_RD_DEPTH))
2042                  begin
2043                    //Read the value from the FIFO
2044                    read_fifo;
2045                    next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH;
2046
2047                    //Acknowledge the read from the FIFO, no error
2048                    ideal_valid        <= 1'b1;
2049                    //Not close to empty
2050                    ideal_empty        <= 1'b0;
2051                    ideal_almost_empty <= 1'b0;
2052
2053                    ideal_rd_count     <= num_read_words_sized_i;
2054
2055                  end // if ((tmp_rd_listsize > 2) && (tmp_rd_listsize<=C_FIFO_RD_DEPTH-1))
2056
2057                //If the FIFO is two from empty
2058                else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 2)
2059                  begin
2060                    //Read the value from the FIFO
2061                    read_fifo;
2062                    next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH;
2063
2064                    //Acknowledge the read from the FIFO, no error
2065                    ideal_valid        <= 1'b1;
2066                    //Fifo is not yet empty. It is going almost_empty
2067                    ideal_empty        <= 1'b0;
2068                    ideal_almost_empty <= 1'b1;
2069
2070                    ideal_rd_count     <= num_read_words_sized_i;
2071
2072                  end // if (tmp_rd_listsize == 2)
2073
2074                //If the FIFO is one from empty
2075                else if ((tmp_rd_listsize/C_DEPTH_RATIO_WR == 1))
2076                  begin
2077                    //Read the value from the FIFO
2078                    read_fifo;
2079                    next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH;
2080
2081                    //Acknowledge the read from the FIFO, no error
2082                    ideal_valid        <= 1'b1;
2083                    //Note that FIFO is GOING empty
2084                    ideal_empty        <= 1'b1;
2085                    ideal_almost_empty <= 1'b1;
2086
2087                    ideal_rd_count     <= num_read_words_sized_i;
2088
2089                  end // if (tmp_rd_listsize == 1)
2090
2091
2092                //If the FIFO is completely empty
2093                else if (tmp_rd_listsize/C_DEPTH_RATIO_WR <= 0)
2094                  begin
2095                    //Do not change the contents of the FIFO
2096
2097                    //Do not acknowledge the read from empty FIFO
2098                    ideal_valid        <= 1'b0;
2099                    //Reminder that FIFO is still empty
2100                    ideal_empty        <= 1'b1;
2101                    ideal_almost_empty <= 1'b1;
2102
2103                    ideal_rd_count     <= num_read_words_sized_i;
2104
2105                  end // if (tmp_rd_listsize <= 0)
2106
2107              end // if (ideal_empty == 1'b0)
2108
2109            end //(RD_EN == 1'b1)
2110
2111          else //if (RD_EN == 1'b0)
2112            begin
2113              //If user did not attempt a read, do not give an ack or err
2114              ideal_valid          <= 1'b0;
2115
2116              //Check for empty
2117              if (tmp_rd_listsize/C_DEPTH_RATIO_WR <= 0)
2118                ideal_empty        <= 1'b1;
2119              else
2120                ideal_empty        <= 1'b0;
2121
2122              //Check for almost_empty
2123              if (tmp_rd_listsize/C_DEPTH_RATIO_WR <= 1)
2124                ideal_almost_empty <= 1'b1;
2125              else
2126                ideal_almost_empty <= 1'b0;
2127
2128              ideal_rd_count       <= num_read_words_sized_i;
2129
2130            end // else: !if(RD_EN == 1'b1)
2131
2132        /*****************************************************************/
2133        // Read Operation - Read Latency 0
2134        /*****************************************************************/
2135        end else if (C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0) begin
2136          if (RD_EN == 1'b1) begin
2137
2138            if (ideal_empty == 1'b1) begin
2139
2140              //If the FIFO is completely empty, and is reporting empty
2141              if (tmp_rd_listsize/C_DEPTH_RATIO_WR <= 0) begin
2142                //Do not change the contents of the FIFO
2143
2144                //Do not acknowledge the read from empty FIFO
2145                ideal_valid        <= 1'b0;
2146                //Reminder that FIFO is still empty
2147                ideal_empty        <= 1'b1;
2148                ideal_almost_empty <= 1'b1;
2149
2150                ideal_rd_count     <= num_read_words_sized_i;
2151
2152              //If the FIFO is one from empty, but it is reporting empty
2153              end else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 1) begin
2154                //Do not change the contents of the FIFO
2155
2156                //Do not acknowledge the read from empty FIFO
2157                ideal_valid        <= 1'b0;
2158                //Note that FIFO is no longer empty, but is almost empty (has one word left)
2159                ideal_empty        <= 1'b0;
2160                ideal_almost_empty <= 1'b1;
2161
2162                ideal_rd_count     <= num_read_words_sized_i;
2163
2164              //If the FIFO is two from empty, and is reporting empty
2165              end else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 2) begin
2166                //Do not change the contents of the FIFO
2167
2168                //Do not acknowledge the read from empty FIFO
2169                ideal_valid        <= 1'b0;
2170                //Fifo has two words, so is neither empty or almost empty
2171                ideal_empty        <= 1'b0;
2172                ideal_almost_empty <= 1'b0;
2173
2174                ideal_rd_count     <= num_read_words_sized_i;
2175
2176                //If the FIFO is not close to empty, but is reporting that it is
2177              // Treat the FIFO as empty this time, but unset EMPTY flags.
2178              end else if ((tmp_rd_listsize/C_DEPTH_RATIO_WR > 2) &&
2179                          (tmp_rd_listsize/C_DEPTH_RATIO_WR<C_FIFO_RD_DEPTH)) begin
2180                //Do not change the contents of the FIFO
2181
2182                //Do not acknowledge the read from empty FIFO
2183                ideal_valid        <= 1'b0;
2184                //Note that the FIFO is No Longer Empty or Almost Empty
2185                ideal_empty        <= 1'b0;
2186                ideal_almost_empty <= 1'b0;
2187
2188                ideal_rd_count     <= num_read_words_sized_i;
2189
2190              end // if ((tmp_rd_listsize > 2) && (tmp_rd_listsize<=C_FIFO_RD_DEPTH-1))
2191
2192            end else begin
2193
2194              //If the FIFO is completely full, and we are successfully reading from it
2195              if (tmp_rd_listsize/C_DEPTH_RATIO_WR >= C_FIFO_RD_DEPTH) begin
2196                //Read the value from the FIFO
2197                read_fifo;
2198                next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH;
2199
2200                //Acknowledge the read from the FIFO, no error
2201                ideal_valid        <= 1'b1;
2202                //Not close to empty
2203                ideal_empty        <= 1'b0;
2204                ideal_almost_empty <= 1'b0;
2205
2206                ideal_rd_count     <= num_read_words_sized_i;
2207
2208              //If the FIFO is not close to being empty
2209              end else if ((tmp_rd_listsize/C_DEPTH_RATIO_WR > 2) &&
2210                           (tmp_rd_listsize/C_DEPTH_RATIO_WR<=C_FIFO_RD_DEPTH)) begin
2211                //Read the value from the FIFO
2212                read_fifo;
2213                next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH;
2214
2215                //Acknowledge the read from the FIFO, no error
2216                ideal_valid        <= 1'b1;
2217                //Not close to empty
2218                ideal_empty        <= 1'b0;
2219                ideal_almost_empty <= 1'b0;
2220
2221                ideal_rd_count     <= num_read_words_sized_i;
2222
2223              //If the FIFO is two from empty
2224              end else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 2) begin
2225                //Read the value from the FIFO
2226                read_fifo;
2227                next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH;
2228
2229                //Acknowledge the read from the FIFO, no error
2230                ideal_valid        <= 1'b1;
2231                //Fifo is not yet empty. It is going almost_empty
2232                ideal_empty        <= 1'b0;
2233                ideal_almost_empty <= 1'b1;
2234
2235                ideal_rd_count     <= num_read_words_sized_i;
2236
2237              //If the FIFO is one from empty
2238              end else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 1) begin
2239                //Read the value from the FIFO
2240                read_fifo;
2241                next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH;
2242
2243                //Acknowledge the read from the FIFO, no error
2244                ideal_valid        <= 1'b1;
2245                //Note that FIFO is GOING empty
2246                ideal_empty        <= 1'b1;
2247                ideal_almost_empty <= 1'b1;
2248
2249                ideal_rd_count     <= num_read_words_sized_i;
2250
2251              //If the FIFO is completely empty
2252              end else if (tmp_rd_listsize/C_DEPTH_RATIO_WR <= 0) begin
2253                //Do not change the contents of the FIFO
2254
2255                //Do not acknowledge the read from empty FIFO
2256                ideal_valid        <= 1'b0;
2257                //Reminder that FIFO is still empty
2258                ideal_empty        <= 1'b1;
2259                ideal_almost_empty <= 1'b1;
2260
2261                ideal_rd_count     <= num_read_words_sized_i;
2262
2263              end // if (tmp_rd_listsize <= 0)
2264
2265            end // if (ideal_empty == 1'b0)
2266
2267          end else begin//(RD_EN == 1'b0)
2268
2269
2270            //If user did not attempt a read, do not give an ack or err
2271            ideal_valid           <= 1'b0;
2272
2273            //Check for empty
2274            if (tmp_rd_listsize/C_DEPTH_RATIO_WR <= 0)
2275              ideal_empty         <= 1'b1;
2276            else
2277              ideal_empty         <= 1'b0;
2278
2279            //Check for almost_empty
2280            if (tmp_rd_listsize/C_DEPTH_RATIO_WR <= 1)
2281              ideal_almost_empty  <= 1'b1;
2282            else
2283              ideal_almost_empty  <= 1'b0;
2284
2285            ideal_rd_count        <= num_read_words_sized_i;
2286
2287          end // else: !if(RD_EN == 1'b1)
2288        end //if (C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0)
2289
2290
2291        /*********************************************************
2292         * Programmable EMPTY flags
2293         *********************************************************/
2294        //Determine the Assert and Negate thresholds for Programmable Empty
2295        //  (Subtract 2 read-sized words when using Preload 0)
2296
2297        //Single Programmable Empty Constant Threshold
2298        if (C_PROG_EMPTY_TYPE==1) begin
2299          if (C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0) begin
2300            prog_empty_actual_thresh_assert = C_PROG_EMPTY_THRESH_ASSERT_VAL-2;
2301            prog_empty_actual_thresh_negate = C_PROG_EMPTY_THRESH_ASSERT_VAL-2;
2302          end
2303          else begin
2304            prog_empty_actual_thresh_assert = C_PROG_EMPTY_THRESH_ASSERT_VAL;
2305            prog_empty_actual_thresh_negate = C_PROG_EMPTY_THRESH_ASSERT_VAL;
2306          end
2307
2308        //Two Programmable Empty Constant Thresholds
2309        end else if (C_PROG_EMPTY_TYPE==2) begin
2310          if (C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0) begin
2311            prog_empty_actual_thresh_assert = C_PROG_EMPTY_THRESH_ASSERT_VAL-2;
2312            prog_empty_actual_thresh_negate = C_PROG_EMPTY_THRESH_NEGATE_VAL-2;
2313          end
2314          else begin
2315            prog_empty_actual_thresh_assert = C_PROG_EMPTY_THRESH_ASSERT_VAL;
2316            prog_empty_actual_thresh_negate = C_PROG_EMPTY_THRESH_NEGATE_VAL;
2317          end
2318
2319        //Single Programmable Empty Constant Threshold
2320        end else if (C_PROG_EMPTY_TYPE==3) begin
2321          if (C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0) begin
2322            prog_empty_actual_thresh_assert = PROG_EMPTY_THRESH-2;
2323            prog_empty_actual_thresh_negate = PROG_EMPTY_THRESH-2;
2324          end
2325          else begin
2326            prog_empty_actual_thresh_assert = PROG_EMPTY_THRESH;
2327            prog_empty_actual_thresh_negate = PROG_EMPTY_THRESH;
2328
2329          end
2330        //Two Programmable Empty Constant Thresholds
2331        end else if (C_PROG_EMPTY_TYPE==4) begin
2332          if (C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0) begin
2333            prog_empty_actual_thresh_assert = PROG_EMPTY_THRESH_ASSERT-2;
2334            prog_empty_actual_thresh_negate = PROG_EMPTY_THRESH_NEGATE-2;
2335          end
2336          else begin
2337            prog_empty_actual_thresh_assert = PROG_EMPTY_THRESH_ASSERT;
2338            prog_empty_actual_thresh_negate = PROG_EMPTY_THRESH_NEGATE;
2339          end
2340        end
2341
2342        if ((num_read_words_pe/C_DEPTH_RATIO_WR == prog_empty_actual_thresh_assert+1)
2343            && RD_EN) begin
2344          prog_empty_d <= 1'b1;
2345        end else if (num_read_words_pe/C_DEPTH_RATIO_WR
2346                     <= prog_empty_actual_thresh_assert) begin
2347          prog_empty_d <= 1'b1;
2348        end else if (num_read_words_pe/C_DEPTH_RATIO_WR
2349                     > prog_empty_actual_thresh_negate) begin
2350          prog_empty_d <= 1'b0;
2351        end
2352
2353
2354        ideal_prog_empty <= prog_empty_d;
2355        num_rd_bits      <= next_num_rd_bits;
2356        wr_ptr_rdclk     <= wr_ptr;
2357      end //rd_rst_i==0
2358    end //always
2359
2360 endmodule // fifo_generator_v4_3_bhv_ver_as
2361
2362
2363 /*******************************************************************************
2364  * Declaration of top-level module
2365  ******************************************************************************/
2366 module fifo_generator_v4_3_bhv_ver_ss
2367   (
2368    CLK, RST, SRST, DIN, WR_EN, RD_EN,
2369    PROG_FULL_THRESH, PROG_FULL_THRESH_ASSERT, PROG_FULL_THRESH_NEGATE,
2370    PROG_EMPTY_THRESH, PROG_EMPTY_THRESH_ASSERT, PROG_EMPTY_THRESH_NEGATE,
2371    DOUT, FULL, ALMOST_FULL, WR_ACK, OVERFLOW, EMPTY,
2372    ALMOST_EMPTY, VALID, UNDERFLOW, DATA_COUNT,
2373    PROG_FULL, PROG_EMPTY
2374    );
2375
2376    /**************************************************************************
2377     * Declare user parameters and their defaults
2378     *************************************************************************/
2379    parameter  C_DATA_COUNT_WIDTH             = 2;
2380    parameter  C_DIN_WIDTH                    = 8;
2381    parameter  C_DOUT_RST_VAL                 = "";
2382    parameter  C_DOUT_WIDTH                   = 8;
2383    parameter  C_FULL_FLAGS_RST_VAL           = 1;
2384    parameter  C_HAS_ALMOST_EMPTY             = 0;
2385    parameter  C_HAS_ALMOST_FULL              = 0;
2386    parameter  C_HAS_DATA_COUNT               = 0;
2387    parameter  C_HAS_OVERFLOW                 = 0;
2388    parameter  C_HAS_RD_DATA_COUNT            = 0;
2389    parameter  C_HAS_RST                      = 0;
2390    parameter  C_HAS_SRST                     = 0;
2391    parameter  C_HAS_UNDERFLOW                = 0;
2392    parameter  C_HAS_VALID                    = 0;
2393    parameter  C_HAS_WR_ACK                   = 0;
2394    parameter  C_HAS_WR_DATA_COUNT            = 0;
2395    parameter  C_IMPLEMENTATION_TYPE          = 0;
2396    parameter  C_MEMORY_TYPE                  = 1;
2397    parameter  C_OVERFLOW_LOW                 = 0;
2398    parameter  C_PRELOAD_LATENCY              = 1;
2399    parameter  C_PRELOAD_REGS                 = 0;
2400    parameter  C_PROG_EMPTY_THRESH_ASSERT_VAL = 0;
2401    parameter  C_PROG_EMPTY_THRESH_NEGATE_VAL = 0;
2402    parameter  C_PROG_EMPTY_TYPE              = 0;
2403    parameter  C_PROG_FULL_THRESH_ASSERT_VAL  = 0;
2404    parameter  C_PROG_FULL_THRESH_NEGATE_VAL  = 0;
2405    parameter  C_PROG_FULL_TYPE               = 0;
2406    parameter  C_RD_DATA_COUNT_WIDTH          = 2;
2407    parameter  C_RD_DEPTH                     = 256;
2408    parameter  C_RD_PNTR_WIDTH                = 8;
2409    parameter  C_UNDERFLOW_LOW                = 0;
2410    parameter  C_USE_DOUT_RST                 = 0;
2411    parameter  C_USE_EMBEDDED_REG             = 0;
2412    parameter  C_USE_FWFT_DATA_COUNT          = 0;
2413    parameter  C_VALID_LOW                    = 0;
2414    parameter  C_WR_ACK_LOW                   = 0;
2415    parameter  C_WR_DATA_COUNT_WIDTH          = 2;
2416    parameter  C_WR_DEPTH                     = 256;
2417    parameter  C_WR_PNTR_WIDTH                = 8;
2418
2419
2420    /**************************************************************************
2421     * Declare Input and Output Ports
2422     *************************************************************************/
2423    //Inputs
2424    input      CLK;
2425    input [C_DIN_WIDTH-1:0] DIN;
2426    input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH;
2427    input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_ASSERT;
2428    input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_NEGATE;
2429    input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH;
2430    input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_ASSERT;
2431    input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_NEGATE;
2432    input                       RD_EN;
2433    input                       RST;
2434    input                       SRST;
2435    input                       WR_EN;
2436
2437    //Outputs
2438    output                      ALMOST_EMPTY;
2439    output                      ALMOST_FULL;
2440    output [C_DATA_COUNT_WIDTH-1:0] DATA_COUNT;
2441    output [C_DOUT_WIDTH-1:0]       DOUT;
2442    output                          EMPTY;
2443    output                          FULL;
2444    output                          OVERFLOW;
2445    output                          PROG_EMPTY;
2446    output                          PROG_FULL;
2447    output                          VALID;
2448    output                          UNDERFLOW;
2449    output                          WR_ACK;
2450
2451   /*************************************************************************
2452    * Declare the type for each Input/Output port, and connect each I/O
2453    * to it's associated internal signal in the behavioral model
2454    *
2455    * The values for the outputs are assigned in assign statements immediately
2456    * following wire, parameter, and function declarations in this code.
2457    *************************************************************************/
2458    //Inputs
2459    wire CLK;
2460    wire [C_DIN_WIDTH-1:0] DIN;
2461    wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH;
2462    wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_ASSERT;
2463    wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_NEGATE;
2464    wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH;
2465    wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_ASSERT;
2466    wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_NEGATE;
2467    wire RD_EN;
2468    wire RST;
2469    wire SRST;
2470    wire WR_EN;
2471
2472    //Outputs
2473    wire ALMOST_EMPTY;
2474    wire ALMOST_FULL;
2475    reg [C_DATA_COUNT_WIDTH-1:0] DATA_COUNT;
2476    wire [C_DOUT_WIDTH-1:0] DOUT;
2477    wire EMPTY;
2478    wire FULL;
2479    wire OVERFLOW;
2480    wire PROG_EMPTY;
2481    wire PROG_FULL;
2482    wire VALID;
2483    wire UNDERFLOW;
2484    wire WR_ACK;
2485
2486
2487    /***************************************************************************
2488     * Parameters used as constants
2489     **************************************************************************/
2490    //When RST is present, set FULL reset value to '1'.
2491    //If core has no RST, make sure FULL powers-on as '0'.
2492    //The reset value assignments for FULL, ALMOST_FULL, and PROG_FULL are not
2493    //changed for v3.2(IP2_Im). When the core has Sync Reset, C_HAS_SRST=1 and C_HAS_RST=0.
2494    // Therefore, during SRST, all the FULL flags reset to 0.
2495    parameter                      C_HAS_FAST_FIFO = 0;
2496    parameter                      C_FIFO_WR_DEPTH = C_WR_DEPTH;
2497    parameter                      C_FIFO_RD_DEPTH = C_RD_DEPTH;
2498
2499   /**************************************************************************
2500     * FIFO Contents Tracking and Data Count Calculations
2501     *************************************************************************/
2502    //Memory which will be used to simulate a FIFO
2503    reg [C_DIN_WIDTH-1:0]          memory[C_WR_DEPTH-1:0];
2504
2505    //The amount of data stored in the FIFO at any time is given
2506    // by num_bits.
2507    //num_bits is calculated by from the total words in the FIFO.
2508    reg [31:0]                     num_bits;
2509
2510    //The write pointer - tracks write operations
2511    // (Works opposite to core: wr_ptr is a DOWN counter)
2512    reg [31:0]                     wr_ptr;
2513
2514    //The write pointer - tracks read operations
2515    // (Works opposite to core: rd_ptr is a DOWN counter)
2516    reg [31:0]                     rd_ptr;
2517
2518    /**************************
2519     * Data Count
2520     *************************/
2521    //Amount of data stored in the FIFO scaled to read words
2522    wire [31:0]                    num_read_words  = num_bits/C_DOUT_WIDTH;
2523    //num_read_words delayed 1 clock cycle
2524    reg [31:0]                     num_read_words_q;
2525
2526    //Amount of data stored in the FIFO scaled to write words
2527    wire [31:0]                    num_write_words = num_bits/C_DIN_WIDTH;
2528    //num_write_words delayed 1 clock cycle
2529    reg [31:0]                     num_write_words_q;
2530
2531
2532    /**************************************************************************
2533     * Internal Registers and wires
2534     *************************************************************************/
2535
2536    //Temporary signals used for calculating the model's outputs. These
2537    //are only used in the assign statements immediately following wire,
2538    //parameter, and function declarations.
2539    wire                           underflow_i;
2540    wire                           valid_i;
2541    wire                           valid_out;
2542
2543    //Ideal FIFO signals. These are the raw output of the behavioral model,
2544    //which behaves like an ideal FIFO.
2545    reg [C_DOUT_WIDTH-1:0]         ideal_dout;
2546    reg [C_DOUT_WIDTH-1:0]         ideal_dout_d1;
2547    wire [C_DOUT_WIDTH-1:0]        ideal_dout_out;
2548    reg                            ideal_wr_ack;
2549    reg                            ideal_valid;
2550    reg                            ideal_overflow;
2551    reg                            ideal_underflow;
2552    reg                            ideal_full;
2553    reg                            ideal_empty;
2554    reg                            ideal_almost_full;
2555    reg                            ideal_almost_empty;
2556    reg                            ideal_prog_full;
2557    reg                            ideal_prog_empty;
2558
2559    //Assorted reg values for delayed versions of signals
2560    reg                            valid_d1;
2561    reg                            prog_full_d;
2562    reg                            prog_empty_d;
2563
2564
2565    //Internal reset signals
2566    reg                            rst_asreg    =0;
2567    reg                            rst_asreg_d1 =0;
2568    reg                            rst_asreg_d2 =0;
2569    reg                            rst_reg      =0;
2570    reg                            rst_d1       =0;
2571    wire                           rst_comb;
2572    wire                           rst_i;
2573    wire                           srst_i;
2574
2575    //Delayed version of RST
2576    reg                             rst_q;
2577    reg                             rst_qq;
2578
2579    //user specified value for reseting the size of the fifo
2580    reg [C_DOUT_WIDTH-1:0]          dout_reset_val;
2581
2582
2583    /****************************************************************************
2584     * Function Declarations
2585     ***************************************************************************/
2586
2587   /**************************************************************************
2588    * write_fifo
2589    *   This task writes a word to the FIFO memory and updates the
2590    * write pointer.
2591    *   FIFO size is relative to write domain.
2592   ***************************************************************************/
2593    task write_fifo;
2594       begin
2595          memory[wr_ptr]     <= DIN;
2596          if (wr_ptr == 0) begin
2597             wr_ptr          <= C_WR_DEPTH - 1;
2598          end else begin
2599             wr_ptr          <= wr_ptr - 1;
2600          end
2601       end
2602    endtask // write_fifo
2603
2604   /**************************************************************************
2605    * read_fifo
2606    *   This task reads a word from the FIFO memory and updates the read
2607    * pointer. It's output is the ideal_dout bus.
2608    *   FIFO size is relative to write domain.
2609    ***************************************************************************/
2610    task  read_fifo;
2611       begin
2612          ideal_dout <= memory[rd_ptr];
2613          if (rd_ptr == 0) begin
2614             rd_ptr  <= C_RD_DEPTH - 1;
2615          end else begin
2616             rd_ptr  <= rd_ptr - 1;
2617          end
2618       end
2619    endtask
2620
2621    /****************************************************************************
2622     * log2_val
2623     *   Returns the 'log2' value for the input value for the supported ratios
2624     ***************************************************************************/
2625     function [31:0] log2_val;
2626     input [31:0] binary_val;
2627
2628     begin
2629        if (binary_val == 8) begin
2630           log2_val = 3;
2631        end else if (binary_val == 4) begin
2632           log2_val = 2;
2633        end else begin
2634           log2_val = 1;
2635        end
2636     end
2637     endfunction
2638
2639    /****************************************************************************
2640     * hexstr_conv
2641     *   Converts a string of type hex to a binary value (for C_DOUT_RST_VAL)
2642     ***************************************************************************/
2643     function [C_DOUT_WIDTH-1:0] hexstr_conv;
2644     input [(C_DOUT_WIDTH*8)-1:0] def_data;
2645
2646     integer index,i,j;
2647     reg [3:0] bin;
2648
2649     begin
2650       index = 0;
2651       hexstr_conv = 'b0;
2652       for( i=C_DOUT_WIDTH-1; i>=0; i=i-1 )
2653       begin
2654         case (def_data[7:0])
2655           8'b00000000 :
2656           begin
2657             bin = 4'b0000;
2658             i = -1;
2659           end
2660           8'b00110000 : bin = 4'b0000;
2661           8'b00110001 : bin = 4'b0001;
2662           8'b00110010 : bin = 4'b0010;
2663           8'b00110011 : bin = 4'b0011;
2664           8'b00110100 : bin = 4'b0100;
2665           8'b00110101 : bin = 4'b0101;
2666           8'b00110110 : bin = 4'b0110;
2667           8'b00110111 : bin = 4'b0111;
2668           8'b00111000 : bin = 4'b1000;
2669           8'b00111001 : bin = 4'b1001;
2670           8'b01000001 : bin = 4'b1010;
2671           8'b01000010 : bin = 4'b1011;
2672           8'b01000011 : bin = 4'b1100;
2673           8'b01000100 : bin = 4'b1101;
2674           8'b01000101 : bin = 4'b1110;
2675           8'b01000110 : bin = 4'b1111;
2676           8'b01100001 : bin = 4'b1010;
2677           8'b01100010 : bin = 4'b1011;
2678           8'b01100011 : bin = 4'b1100;
2679           8'b01100100 : bin = 4'b1101;
2680           8'b01100101 : bin = 4'b1110;
2681           8'b01100110 : bin = 4'b1111;
2682           default :
2683           begin
2684             bin = 4'bx;
2685           end
2686         endcase
2687         for( j=0; j<4; j=j+1)
2688         begin
2689           if ((index*4)+j < C_DOUT_WIDTH)
2690           begin
2691             hexstr_conv[(index*4)+j] = bin[j];
2692           end
2693         end
2694         index = index + 1;
2695         def_data = def_data >> 8;
2696       end
2697     end
2698   endfunction
2699
2700
2701   /*************************************************************************
2702   * Initialize Signals for clean power-on simulation
2703   *************************************************************************/
2704    initial begin
2705       num_bits           = 0;
2706       num_read_words_q   = 0;
2707       num_write_words_q  = 0;
2708       rd_ptr             = C_RD_DEPTH -1;
2709       wr_ptr             = C_WR_DEPTH -1;
2710       dout_reset_val     = hexstr_conv(C_DOUT_RST_VAL);
2711       ideal_dout       = dout_reset_val;
2712       ideal_wr_ack       = 1'b0;
2713       ideal_valid        = 1'b0;
2714       valid_d1           = 1'b0;
2715       ideal_overflow     = 1'b0;
2716       ideal_underflow    = 1'b0;
2717       ideal_full         = 1'b0;
2718       ideal_empty        = 1'b1;
2719       ideal_almost_full  = 1'b0;
2720       ideal_almost_empty = 1'b1;
2721       ideal_prog_full    = 1'b0;
2722       ideal_prog_empty   = 1'b1;
2723       prog_full_d        = 1'b0;
2724       prog_empty_d       = 1'b1;
2725       rst_q              = 1'b0;
2726       rst_qq             = 1'b0;
2727    end
2728
2729
2730   /*************************************************************************
2731    * Connect the module inputs and outputs to the internal signals of the
2732    * behavioral model.
2733    *************************************************************************/
2734    //Inputs
2735    /*
2736    wire CLK;
2737    wire [C_DIN_WIDTH-1:0] DIN;
2738    wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH;
2739    wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_ASSERT;
2740    wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_NEGATE;
2741    wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH;
2742    wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_ASSERT;
2743    wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_NEGATE;
2744    wire RD_EN;
2745    wire RST;
2746    wire WR_EN;
2747     */
2748
2749   //Outputs
2750   assign ALMOST_EMPTY  = ideal_almost_empty;
2751   assign ALMOST_FULL   = ideal_almost_full;
2752
2753   //Dout may change behavior based on latency
2754   assign ideal_dout_out= (C_USE_EMBEDDED_REG==1 &&
2755                           (C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1))?
2756                          ideal_dout_d1: ideal_dout;
2757   assign DOUT = ideal_dout_out;
2758
2759   assign EMPTY         = ideal_empty;
2760   assign FULL          = ideal_full;
2761
2762   //Overflow may be active-low
2763   assign OVERFLOW      = ideal_overflow ? !C_OVERFLOW_LOW : C_OVERFLOW_LOW;
2764
2765   assign PROG_EMPTY    = ideal_prog_empty;
2766   assign PROG_FULL     = ideal_prog_full;
2767
2768    //Valid may change behavior based on latency or active-low
2769   assign valid_i       = (C_PRELOAD_LATENCY==0) ? (RD_EN & ~EMPTY) : ideal_valid;
2770   assign valid_out     = (C_PRELOAD_LATENCY==2 &&
2771                           (C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1))?
2772                          valid_d1: valid_i;
2773   assign VALID         = valid_out ? !C_VALID_LOW : C_VALID_LOW;
2774
2775   //Trim data count differently depending on set widths
2776   always @(num_read_words) begin
2777      if (C_DATA_COUNT_WIDTH>C_RD_PNTR_WIDTH) begin
2778         DATA_COUNT = num_read_words[C_RD_PNTR_WIDTH:0];
2779      end else begin
2780         DATA_COUNT =
2781           num_read_words[C_RD_PNTR_WIDTH-1:C_RD_PNTR_WIDTH-C_DATA_COUNT_WIDTH];
2782      end //if
2783   end //always
2784
2785   //Underflow may change behavior based on latency or active-low
2786   assign underflow_i   = (C_PRELOAD_LATENCY==0) ? (RD_EN & EMPTY) : ideal_underflow;
2787   assign UNDERFLOW     = underflow_i ? !C_UNDERFLOW_LOW : C_UNDERFLOW_LOW;
2788
2789
2790   //Write acknowledge may be active low
2791   assign WR_ACK        = ideal_wr_ack ? !C_WR_ACK_LOW : C_WR_ACK_LOW;
2792
2793
2794
2795   /*****************************************************************************
2796    * Internal reset logic
2797    ****************************************************************************/
2798   assign srst_i        = C_HAS_SRST ? SRST : 0;
2799   assign rst_comb      = !rst_asreg_d2 && rst_asreg;
2800   assign rst_i         = C_HAS_RST ? rst_reg : 0;
2801
2802   always @(posedge CLK or posedge RST) begin
2803      if (RST == 1'b1) begin
2804        rst_asreg <= 1'b1;
2805      end else begin
2806        if (rst_asreg_d1 == 1'b1) begin
2807          rst_asreg <= 1'b0;
2808        end else begin
2809          rst_asreg <= rst_asreg;
2810        end
2811      end
2812   end
2813
2814   always @(posedge CLK) begin
2815      rst_asreg_d1 <= rst_asreg;
2816      rst_asreg_d2 <= rst_asreg_d1;
2817   end
2818
2819   always @(posedge CLK or posedge rst_comb) begin
2820      if (rst_comb == 1'b1) begin
2821        rst_reg <= 1'b1;
2822      end else begin
2823        rst_reg <= 1'b0;
2824      end
2825   end
2826
2827    /**************************************************************************
2828     * Assorted registers for delayed versions of signals
2829     **************************************************************************/
2830    //Capture delayed version of valid
2831    always @(posedge CLK or posedge rst_i) begin
2832       if (rst_i == 1'b1) begin
2833          valid_d1 <= 1'b0;
2834       end else begin
2835          if (srst_i) begin
2836             valid_d1 <= 1'b0;
2837          end else begin
2838             valid_d1 <= valid_i;
2839          end
2840       end
2841    end // always @ (posedge CLK or posedge rst_i)
2842
2843    //Capture delayed version of dout
2844    always @(posedge CLK or posedge rst_i) begin
2845       if (rst_i == 1'b1 && C_USE_DOUT_RST == 1) begin
2846          ideal_dout_d1 <= dout_reset_val;
2847       end else begin
2848          if (srst_i && C_USE_DOUT_RST == 1) begin
2849             ideal_dout_d1 <= dout_reset_val;
2850          end else begin
2851             ideal_dout_d1 <= ideal_dout;
2852          end
2853       end
2854    end
2855
2856    /**************************************************************************
2857     * Overflow and Underflow Flag calculation
2858     *  (handled separately because they don't support rst)
2859     **************************************************************************/
2860    always @(posedge CLK) begin
2861      ideal_overflow    <= WR_EN & ideal_full;
2862      ideal_underflow   <= ideal_empty & RD_EN;
2863    end
2864
2865    /*************************************************************************
2866     * Write and Read Logic
2867     ************************************************************************/
2868    always @(posedge CLK or posedge rst_i)
2869      begin : gen_wr_ack_resp
2870
2871         //Register reset
2872         rst_q   <= rst_i;
2873         rst_qq  <= rst_q;
2874
2875      end // block: gen_wr_ack_resp
2876
2877    // block memory has a synchronous reset
2878    always @(posedge CLK) begin : gen_fifo_blkmemdout
2879       //Changed the latency of during async reset to '1' instead of '2' to
2880       // make it consistent with the core.
2881       if (rst_i || rst_q || srst_i) begin
2882          /******Initialize Read Domain Signals*********************************/
2883          if (C_MEMORY_TYPE == 1 && C_USE_DOUT_RST == 1) begin
2884             ideal_dout <= dout_reset_val;
2885          end
2886       end
2887    end //always
2888
2889    always @(posedge CLK or posedge rst_i) begin : gen_fifo
2890
2891       /****** Reset fifo - Asynchronous Reset**********************************/
2892       //Changed the latency of during async reset to '1' instead of '2' to
2893       // make it consistent with the core.
2894       if (rst_i) begin //v3.2
2895          /******Initialize Generic FIFO constructs*****************************/
2896          num_bits           <= 0;
2897          wr_ptr             <= C_WR_DEPTH - 1;
2898          rd_ptr             <= C_RD_DEPTH - 1;
2899          num_read_words_q   <= 0;
2900          num_write_words_q  <= 0;
2901
2902
2903          /******Initialize Write Domain Signals********************************/
2904          ideal_wr_ack       <= 0;
2905          ideal_full         <= C_FULL_FLAGS_RST_VAL;
2906          ideal_almost_full  <= C_FULL_FLAGS_RST_VAL;
2907
2908          /******Initialize Read Domain Signals*********************************/
2909          if (C_MEMORY_TYPE != 1 && C_USE_DOUT_RST == 1) begin
2910             ideal_dout      <= dout_reset_val;
2911          end
2912          ideal_valid        <= 1'b0;
2913          ideal_empty        <= 1'b1;
2914          ideal_almost_empty <= 1'b1;
2915
2916       end else begin
2917          if (srst_i) begin
2918             // SRST is available only for Sync BRAM and Sync DRAM.
2919             // Not for SSHFT.
2920             if (C_MEMORY_TYPE == 1 || C_MEMORY_TYPE == 2) begin
2921                /******Initialize Generic FIFO constructs***********************/
2922                num_bits           <= 0;
2923                wr_ptr             <= C_WR_DEPTH - 1;
2924                rd_ptr             <= C_RD_DEPTH - 1;
2925                num_read_words_q   <= 0;
2926                num_write_words_q  <= 0;
2927
2928                /******Initialize Write Domain Signals**************************/
2929                ideal_wr_ack       <= 0;
2930                ideal_full         <= 0; //'0'
2931                ideal_almost_full  <= 0; //'0'
2932
2933                /******Initialize Read Domain Signals***************************/
2934                //Reset DOUT of Sync DRAM. Sync BRAM DOUT was reset in the
2935                // above always block.
2936                if (C_MEMORY_TYPE == 2 && C_USE_DOUT_RST == 1 ) begin
2937                   ideal_dout      <= dout_reset_val;
2938                end
2939                ideal_valid        <= 1'b0;
2940                ideal_empty        <= 1'b1;
2941                ideal_almost_empty <= 1'b1;
2942             end
2943
2944          end else begin  //normal operating conditions
2945          /********************************************************************/
2946          // Synchronous FIFO Condition #1 : Writing and not reading
2947          /********************************************************************/
2948          if (WR_EN & ~RD_EN) begin
2949
2950             /*********************************/
2951             //If the FIFO is full, do NOT perform the write,
2952             // update flags accordingly
2953             /*********************************/
2954             if (num_write_words >= C_FIFO_WR_DEPTH) begin
2955                ideal_wr_ack       <= 0;
2956
2957                //still full
2958                ideal_full         <= 1'b1;
2959                ideal_almost_full  <= 1'b1;
2960
2961                //write unsuccessful - do not change contents
2962
2963                // no read attempted
2964                ideal_valid        <= 1'b0;
2965
2966                //Not near empty
2967                ideal_empty        <= 1'b0;
2968                ideal_almost_empty <= 1'b0;
2969
2970
2971             /*********************************/
2972             //If the FIFO is reporting FULL
2973             // (Startup condition)
2974             /*********************************/
2975             end else if ((num_write_words < C_FIFO_WR_DEPTH) && (ideal_full == 1'b1)) begin
2976                ideal_wr_ack       <= 0;
2977
2978                //still full
2979                ideal_full         <= 1'b0;
2980                ideal_almost_full  <= 1'b0;
2981
2982                //write unsuccessful - do not change contents
2983
2984                // no read attempted
2985                ideal_valid        <= 1'b0;
2986
2987                //FIFO EMPTY in this state can not be determined
2988                //ideal_empty        <= 1'b0;
2989                //ideal_almost_empty <= 1'b0;
2990
2991
2992                /*********************************/
2993                //If the FIFO is one from full
2994                /*********************************/
2995             end else if (num_write_words == C_FIFO_WR_DEPTH-1) begin
2996                //good write
2997                ideal_wr_ack       <= 1;
2998
2999                //FIFO is one from FULL and going FULL
3000                ideal_full         <= 1'b1;
3001                ideal_almost_full  <= 1'b1;
3002
3003                //Add input data
3004                write_fifo;
3005
3006                // no read attempted
3007                ideal_valid        <= 1'b0;
3008
3009                //Not near empty
3010                ideal_empty        <= 1'b0;
3011                ideal_almost_empty <= 1'b0;
3012
3013                num_bits           <= num_bits + C_DIN_WIDTH;
3014
3015                /*********************************/
3016                //If the FIFO is 2 from full
3017                /*********************************/
3018             end else if (num_write_words == C_FIFO_WR_DEPTH-2) begin
3019                //good write
3020                ideal_wr_ack       <= 1;
3021
3022                //2 from full, and writing, so set almost_full
3023                ideal_full         <= 1'b0;
3024                ideal_almost_full  <= 1'b1;
3025
3026                //Add input data
3027                write_fifo;
3028
3029                //no read attempted
3030                ideal_valid        <= 1'b0;
3031
3032                //Not near empty
3033                ideal_empty        <= 1'b0;
3034                ideal_almost_empty <= 1'b0;
3035
3036                num_bits           <= num_bits + C_DIN_WIDTH;
3037
3038                /*********************************/
3039                //If the FIFO is ALMOST EMPTY
3040                /*********************************/
3041             end else if (num_read_words == 1) begin
3042                //good write
3043                ideal_wr_ack       <= 1;
3044
3045                //Not near FULL
3046                ideal_full         <= 1'b0;
3047                ideal_almost_full  <= 1'b0;
3048
3049                //Add input data
3050                write_fifo;
3051
3052                // no read attempted
3053                ideal_valid        <= 1'b0;
3054
3055                //Leaving ALMOST_EMPTY
3056                ideal_empty        <= 1'b0;
3057                ideal_almost_empty <= 1'b0;
3058
3059                num_bits           <= num_bits + C_DIN_WIDTH;
3060
3061                /*********************************/
3062                //If the FIFO is EMPTY
3063                /*********************************/
3064             end else if (num_read_words == 0) begin
3065                // good write
3066                ideal_wr_ack       <= 1;
3067
3068                //Not near FULL
3069                ideal_full         <= 1'b0;
3070                ideal_almost_full  <= 1'b0;
3071
3072                //Add input data
3073                write_fifo;
3074
3075                // no read attempted
3076                ideal_valid        <= 1'b0;
3077
3078                //Leaving EMPTY (still ALMOST_EMPTY)
3079                ideal_empty        <= 1'b0;
3080                ideal_almost_empty <= 1'b1;
3081
3082                num_bits           <= num_bits + C_DIN_WIDTH;
3083
3084                /*********************************/
3085                //If the FIFO is not near EMPTY or FULL
3086                /*********************************/
3087             end else begin
3088                // good write
3089                ideal_wr_ack       <= 1;
3090
3091                //Not near FULL
3092                ideal_full         <= 1'b0;
3093                ideal_almost_full  <= 1'b0;
3094
3095                //Add input data
3096                write_fifo;
3097
3098                // no read attempted
3099                ideal_valid        <= 1'b0;
3100
3101                //Not near EMPTY
3102                ideal_empty        <= 1'b0;
3103                ideal_almost_empty <= 1'b0;
3104
3105                num_bits           <= num_bits + C_DIN_WIDTH;
3106
3107             end // average case
3108
3109
3110             /******************************************************************/
3111             // Synchronous FIFO Condition #2 : Reading and not writing
3112             /******************************************************************/
3113          end else if (~WR_EN & RD_EN) begin
3114
3115             /*********************************/
3116             //If the FIFO is EMPTY
3117             /*********************************/
3118             if ((num_read_words == 0) || (ideal_empty == 1'b1)) begin
3119                //no write attemped
3120                ideal_wr_ack       <= 0;
3121
3122                //FIFO is not near FULL
3123                ideal_full         <= 1'b0;
3124                ideal_almost_full  <= 1'b0;
3125
3126                //Read will fail
3127                ideal_valid        <= 1'b0;
3128
3129                //FIFO is still empty
3130                ideal_empty        <= 1'b1;
3131                ideal_almost_empty <= 1'b1;
3132
3133                //No read
3134
3135                /*********************************/
3136                //If the FIFO is ALMOST EMPTY
3137                /*********************************/
3138             end else if (num_read_words == 1) begin
3139                //no write attempted
3140                ideal_wr_ack       <= 0;
3141
3142                //FIFO is not near FULL
3143                ideal_full         <= 1'b0;
3144                ideal_almost_full  <= 1'b0;
3145
3146                //Read successful
3147                ideal_valid        <= 1'b1;
3148
3149                //This read will make FIFO go empty
3150                ideal_empty        <= 1'b1;
3151                ideal_almost_empty <= 1'b1;
3152
3153                //Get the data from the FIFO
3154                read_fifo;
3155                num_bits           <= num_bits - C_DIN_WIDTH;
3156
3157
3158                /*********************************/
3159                //If the FIFO is 2 from EMPTY
3160                /*********************************/
3161             end else if (num_read_words == 2) begin
3162
3163                //no write attempted
3164                ideal_wr_ack       <= 0;
3165
3166                //FIFO is not near FULL
3167                ideal_full         <= 1'b0;
3168                ideal_almost_full  <= 1'b0;
3169
3170                //Read successful
3171                ideal_valid        <= 1'b1;
3172
3173                //FIFO is going ALMOST_EMPTY
3174                ideal_empty        <= 1'b0;
3175                ideal_almost_empty <= 1'b1;
3176
3177                //Get the data from the FIFO
3178                read_fifo;
3179                num_bits           <= num_bits - C_DOUT_WIDTH;
3180
3181
3182
3183                /*********************************/
3184                //If the FIFO is one from full
3185                /*********************************/
3186             end else if (num_write_words == C_FIFO_WR_DEPTH-1) begin
3187
3188                //no write attempted
3189                ideal_wr_ack       <= 0;
3190
3191                //FIFO is leaving ALMOST FULL
3192                ideal_full         <= 1'b0;
3193                ideal_almost_full  <= 1'b0;
3194
3195                //Read successful
3196                ideal_valid        <= 1'b1;
3197
3198                //Not near empty
3199                ideal_empty        <= 1'b0;
3200                ideal_almost_empty <= 1'b0;
3201
3202                //Read from the FIFO
3203                read_fifo;
3204                num_bits           <= num_bits - C_DOUT_WIDTH;
3205
3206
3207                /*********************************/
3208                // FIFO is FULL
3209                /*********************************/
3210             end else if (num_write_words >= C_FIFO_WR_DEPTH)
3211               begin
3212                  //no write attempted
3213                  ideal_wr_ack       <= 0;
3214
3215                  //FIFO is leaving FULL, but is still ALMOST_FULL
3216                  ideal_full         <= 1'b0;
3217                  ideal_almost_full  <= 1'b1;
3218
3219                  //Read successful
3220                  ideal_valid        <= 1'b1;
3221
3222                  //Not near empty
3223                  ideal_empty        <= 1'b0;
3224                  ideal_almost_empty <= 1'b0;
3225
3226                  //Read from the FIFO
3227                  read_fifo;
3228                  num_bits           <= num_bits - C_DOUT_WIDTH;
3229
3230                  /*********************************/
3231                  //If the FIFO is not near EMPTY or FULL
3232                  /*********************************/
3233               end else begin
3234                  //no write attemped
3235                  ideal_wr_ack       <= 0;
3236
3237                  //Not near empty
3238                  ideal_full         <= 1'b0;
3239                  ideal_almost_full  <= 1'b0;
3240
3241                  //Read successful
3242                  ideal_valid        <= 1'b1;
3243
3244                  //Not near empty
3245                  ideal_empty        <= 1'b0;
3246                  ideal_almost_empty <= 1'b0;
3247
3248                  //Read from the FIFO
3249                  read_fifo;
3250                  num_bits           <= num_bits - C_DOUT_WIDTH;
3251
3252
3253               end // average read
3254
3255
3256             /******************************************************************/
3257             // Synchronous FIFO Condition #3 : Reading and writing
3258             /******************************************************************/
3259          end else if (WR_EN & RD_EN) begin
3260
3261             /*********************************/
3262             // FIFO is FULL
3263             /*********************************/
3264             if (num_write_words >= C_FIFO_WR_DEPTH) begin
3265
3266                ideal_wr_ack       <= 0;
3267
3268                //Read will be successful, so FIFO will leave FULL
3269                ideal_full         <= 1'b0;
3270                ideal_almost_full  <= 1'b1;
3271
3272                //Read successful
3273                ideal_valid        <= 1'b1;
3274
3275                //Not near empty
3276                ideal_empty        <= 1'b0;
3277                ideal_almost_empty <= 1'b0;
3278
3279                //Read from the FIFO
3280                read_fifo;
3281                num_bits           <= num_bits - C_DOUT_WIDTH;
3282
3283
3284             /*********************************/
3285             // FIFO is reporting FULL, but it is empty
3286             // (This is a special case, when coming out of RST
3287             /*********************************/
3288             end else if ((num_write_words == 0) && (ideal_full == 1'b1)) begin
3289
3290                ideal_wr_ack       <= 0;
3291
3292                //Read will be successful, so FIFO will leave FULL
3293                ideal_full         <= 1'b0;
3294                ideal_almost_full  <= 1'b0;
3295
3296                //Read unsuccessful
3297                ideal_valid        <= 1'b0;
3298
3299                //Report empty condition
3300                ideal_empty        <= 1'b1;
3301                ideal_almost_empty <= 1'b1;
3302
3303                //Do not read from empty FIFO
3304                // Read from the FIFO
3305
3306
3307                /*********************************/
3308                //If the FIFO is one from full
3309                /*********************************/
3310             end else if (num_write_words == C_FIFO_WR_DEPTH-1) begin
3311
3312                //Write successful
3313                ideal_wr_ack       <= 1;
3314
3315                //FIFO will remain ALMOST_FULL
3316                ideal_full         <= 1'b0;
3317                ideal_almost_full  <= 1'b1;
3318
3319                // put the data into the FIFO
3320                write_fifo;
3321
3322                //Read successful
3323                ideal_valid        <= 1'b1;
3324
3325                //Not near empty
3326                ideal_empty        <= 1'b0;
3327                ideal_almost_empty <= 1'b0;
3328
3329                //Read from the FIFO
3330                read_fifo;
3331                num_bits           <= num_bits + C_DIN_WIDTH - C_DOUT_WIDTH;
3332
3333                /*********************************/
3334                //If the FIFO is ALMOST EMPTY
3335                /*********************************/
3336             end else if (num_read_words == 1) begin
3337
3338                //Write successful
3339                ideal_wr_ack       <= 1;
3340
3341                // Not near FULL
3342                ideal_full         <= 1'b0;
3343                ideal_almost_full  <= 1'b0;
3344
3345                // put the data into the FIFO
3346                write_fifo;
3347
3348                //Read successful
3349                ideal_valid        <= 1'b1;
3350
3351                //FIFO will stay ALMOST_EMPTY
3352                ideal_empty        <= 1'b0;
3353                ideal_almost_empty <= 1'b1;
3354
3355                //Read from the FIFO
3356                read_fifo;
3357                num_bits           <= num_bits + C_DIN_WIDTH - C_DOUT_WIDTH;
3358
3359
3360                /*********************************/
3361                //If the FIFO is EMPTY
3362                /*********************************/
3363             end else if (num_read_words == 0) begin
3364
3365                //Write successful
3366                ideal_wr_ack       <= 1;
3367
3368                // Not near FULL
3369                ideal_full         <= 1'b0;
3370                ideal_almost_full  <= 1'b0;
3371
3372                // put the data into the FIFO
3373                write_fifo;
3374
3375                //Read will fail
3376                ideal_valid        <= 1'b0;
3377
3378                //FIFO will leave EMPTY
3379                ideal_empty        <= 1'b0;
3380                ideal_almost_empty <= 1'b1;
3381
3382                // No read
3383                num_bits           <= num_bits + C_DIN_WIDTH;
3384
3385
3386                /*********************************/
3387                //If the FIFO is not near EMPTY or FULL
3388                /*********************************/
3389             end else begin
3390
3391                //Write successful
3392                ideal_wr_ack       <= 1;
3393
3394                // Not near FULL
3395                ideal_full         <= 1'b0;
3396                ideal_almost_full  <= 1'b0;
3397
3398                // put the data into the FIFO
3399                write_fifo;
3400
3401                //Read successful
3402                ideal_valid        <= 1'b1;
3403
3404                // Not near EMPTY
3405                ideal_empty        <= 1'b0;
3406                ideal_almost_empty <= 1'b0;
3407
3408                //Read from the FIFO
3409                read_fifo;
3410                num_bits           <= num_bits + C_DIN_WIDTH - C_DOUT_WIDTH;
3411
3412             end // average case
3413
3414             /******************************************************************/
3415             // Synchronous FIFO Condition #4 : Not reading or writing
3416             /******************************************************************/
3417          end else begin
3418
3419             /*********************************/
3420             // FIFO is FULL
3421             /*********************************/
3422             if (num_write_words >= C_FIFO_WR_DEPTH) begin
3423
3424                //No write
3425                ideal_wr_ack       <= 0;
3426                ideal_full         <= 1'b1;
3427                ideal_almost_full  <= 1'b1;
3428
3429                //No read
3430                ideal_valid        <= 1'b0;
3431                ideal_empty        <= 1'b0;
3432                ideal_almost_empty <= 1'b0;
3433
3434                //No change to memory
3435
3436                /*********************************/
3437                //If the FIFO is one from full
3438                /*********************************/
3439             end else if (num_write_words == C_FIFO_WR_DEPTH-1) begin
3440
3441                //No write
3442                ideal_wr_ack       <= 0;
3443                ideal_full         <= 1'b0;
3444                ideal_almost_full  <= 1'b1;
3445
3446                //No read
3447                ideal_valid        <= 1'b0;
3448                ideal_empty        <= 1'b0;
3449                ideal_almost_empty <= 1'b0;
3450
3451                //No change to memory
3452
3453                /*********************************/
3454                //If the FIFO is ALMOST EMPTY
3455                /*********************************/
3456             end else if (num_read_words == 1) begin
3457                //No write
3458                ideal_wr_ack       <= 0;
3459                ideal_full         <= 1'b0;
3460                ideal_almost_full  <= 1'b0;
3461
3462                //No read
3463                ideal_valid        <= 1'b0;
3464                ideal_empty        <= 1'b0;
3465                ideal_almost_empty <= 1'b1;
3466
3467                //No change to memory
3468
3469             end // almost empty
3470
3471
3472             /*********************************/
3473             //If the FIFO is EMPTY
3474             /*********************************/
3475             else if (num_read_words == 0)
3476               begin
3477                  //No write
3478                  ideal_wr_ack       <= 0;
3479                  ideal_full         <= 1'b0;
3480                  ideal_almost_full  <= 1'b0;
3481
3482                  //No read
3483                  ideal_valid        <= 1'b0;
3484                  ideal_empty        <= 1'b1;
3485                  ideal_almost_empty <= 1'b1;
3486
3487                  //No change to memory
3488
3489                  /*********************************/
3490                  //If the FIFO is not near EMPTY or FULL
3491                  /*********************************/
3492               end else begin
3493
3494                  //No write
3495                  ideal_wr_ack       <= 0;
3496                  ideal_full         <= 1'b0;
3497                  ideal_almost_full  <= 1'b0;
3498
3499                  //No read
3500                  ideal_valid        <= 1'b0;
3501                  ideal_empty        <= 1'b0;
3502                  ideal_almost_empty <= 1'b0;
3503
3504                  //No change to memory
3505
3506               end //    average case
3507
3508          end // neither reading or writing
3509
3510          num_read_words_q  <= num_read_words;
3511          num_write_words_q <= num_write_words;
3512
3513          end //normal operating conditions
3514       end
3515
3516    end // block: gen_fifo
3517
3518
3519    always @(posedge CLK or posedge rst_i) begin : gen_fifo_p
3520
3521       /****** Reset fifo - Async Reset****************************************/
3522       //The latency of de-assertion of the flags is reduced by 1 to be
3523       // consistent with the core.
3524       if (rst_i) begin
3525          ideal_prog_full   <= C_FULL_FLAGS_RST_VAL;
3526          ideal_prog_empty  <= 1'b1;
3527          prog_full_d       <= C_FULL_FLAGS_RST_VAL;
3528          prog_empty_d      <= 1'b1;
3529
3530       end else begin
3531          if (srst_i) begin
3532             //SRST is available only for Sync BRAM and Sync DRAM. Not for SSHFT.
3533             if (C_MEMORY_TYPE == 1 || C_MEMORY_TYPE == 2) begin
3534                ideal_prog_full   <= 1'b0;
3535                ideal_prog_empty  <= 1'b1;
3536                prog_full_d       <= 1'b0;
3537                prog_empty_d      <= 1'b1;
3538             end
3539          end else begin
3540
3541             /***************************************************************
3542              * Programmable FULL flags
3543              ****************************************************************/
3544             //calculation for standard fifo and latency =2
3545             if  (! (C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0) ) begin
3546                //Single constant threshold
3547                if (C_PROG_FULL_TYPE == 1) begin
3548                   if ((num_write_words >= C_PROG_FULL_THRESH_ASSERT_VAL-1)
3549                       && WR_EN && !RD_EN) begin
3550                      prog_full_d <= 1'b1;
3551                   end else if (((num_write_words == C_PROG_FULL_THRESH_ASSERT_VAL)
3552                                 && RD_EN && !WR_EN) || (rst_q && !rst_i)) begin
3553                      prog_full_d <= 1'b0;
3554                   end
3555
3556                   //Dual constant thresholds
3557                end else if (C_PROG_FULL_TYPE == 2) begin
3558                   if ((num_write_words == C_PROG_FULL_THRESH_ASSERT_VAL-1)
3559                       && WR_EN && !RD_EN) begin
3560                      prog_full_d <= 1'b1;
3561                   end else if ((num_write_words == C_PROG_FULL_THRESH_NEGATE_VAL)
3562                                && RD_EN && !WR_EN) begin
3563                      prog_full_d <= 1'b0;
3564                   end
3565
3566                   //Single input threshold
3567                end else if (C_PROG_FULL_TYPE == 3) begin
3568                   if ((num_write_words == PROG_FULL_THRESH-1)
3569                       && WR_EN && !RD_EN) begin
3570                      prog_full_d <= 1'b1;
3571                   end else if ((num_write_words == PROG_FULL_THRESH)
3572                                && !WR_EN && RD_EN) begin
3573                      prog_full_d <= 1'b0;
3574                   end else if (num_write_words >= PROG_FULL_THRESH) begin
3575                      prog_full_d <= 1'b1;
3576                   end else if (num_write_words < PROG_FULL_THRESH) begin
3577                      prog_full_d <= 1'b0;
3578                   end
3579
3580                   //Dual input thresholds
3581                end else begin
3582                   if ((num_write_words == PROG_FULL_THRESH_ASSERT-1)
3583                       && WR_EN && !RD_EN) begin
3584                      prog_full_d <= 1'b1;
3585                   end else if ((num_write_words == PROG_FULL_THRESH_NEGATE)
3586                                && !WR_EN && RD_EN)begin
3587                      prog_full_d <= 1'b0;
3588                   end else if (num_write_words >= PROG_FULL_THRESH_ASSERT) begin
3589                      prog_full_d <= 1'b1;
3590                   end else if (num_write_words < PROG_FULL_THRESH_NEGATE) begin
3591                      prog_full_d <= 1'b0;
3592                   end
3593                end
3594             end  // (~ (C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0) )
3595
3596
3597             //calculation for FWFT fifo
3598             if  (C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0)  begin
3599                if (C_PROG_FULL_TYPE == 1) begin
3600                   if ((num_write_words >= C_PROG_FULL_THRESH_ASSERT_VAL-1 - 2)
3601                       && WR_EN && !RD_EN) begin
3602                      prog_full_d <= 1'b1;
3603                   end else if (((num_write_words == C_PROG_FULL_THRESH_ASSERT_VAL - 2)
3604                                 && RD_EN && !WR_EN) || (rst_q && !rst_i)) begin
3605                      prog_full_d <= 1'b0;
3606                   end
3607
3608                   //Dual constant thresholds
3609                end else if (C_PROG_FULL_TYPE == 2) begin
3610                   if ((num_write_words == C_PROG_FULL_THRESH_ASSERT_VAL-1 - 2)
3611                       && WR_EN && !RD_EN) begin
3612                      prog_full_d <= 1'b1;
3613                   end else if ((num_write_words == C_PROG_FULL_THRESH_NEGATE_VAL - 2)
3614                                && RD_EN && !WR_EN) begin
3615                      prog_full_d <= 1'b0;
3616                   end
3617
3618                   //Single input threshold
3619                end else if (C_PROG_FULL_TYPE == 3) begin
3620                   if ((num_write_words == PROG_FULL_THRESH-1 - 2)
3621                       && WR_EN && !RD_EN) begin
3622                      prog_full_d <= 1'b1;
3623                   end else if ((num_write_words == PROG_FULL_THRESH - 2)
3624                                && !WR_EN && RD_EN) begin
3625                      prog_full_d <= 1'b0;
3626                   end else if (num_write_words >= PROG_FULL_THRESH - 2) begin
3627                      prog_full_d <= 1'b1;
3628                   end else if (num_write_words < PROG_FULL_THRESH - 2) begin
3629                      prog_full_d <= 1'b0;
3630                   end
3631
3632                   //Dual input thresholds
3633                end else begin
3634                   if ((num_write_words == PROG_FULL_THRESH_ASSERT-1 - 2)
3635                       && WR_EN && !RD_EN) begin
3636                      prog_full_d <= 1'b1;
3637                   end else if ((num_write_words == PROG_FULL_THRESH_NEGATE - 2)
3638                                && !WR_EN && RD_EN)begin
3639                      prog_full_d <= 1'b0;
3640                   end else if (num_write_words >= PROG_FULL_THRESH_ASSERT - 2) begin
3641                      prog_full_d <= 1'b1;
3642                   end else if (num_write_words < PROG_FULL_THRESH_NEGATE - 2) begin
3643                      prog_full_d <= 1'b0;
3644                   end
3645                end
3646             end  //  (C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0)
3647
3648             /*****************************************************************
3649              * Programmable EMPTY flags
3650              ****************************************************************/
3651             //calculation for standard fifo and latency = 2
3652             if  (! (C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0) ) begin
3653                //Single constant threshold
3654                if (C_PROG_EMPTY_TYPE == 1) begin
3655                   if ((num_read_words == C_PROG_EMPTY_THRESH_ASSERT_VAL+1)
3656                       && RD_EN && !WR_EN) begin
3657                      prog_empty_d <= 1'b1;
3658                   end else if ((num_read_words == C_PROG_EMPTY_THRESH_ASSERT_VAL)
3659                                && WR_EN && !RD_EN) begin
3660                      prog_empty_d <= 1'b0;
3661                end
3662             //Dual constant thresholds
3663             end else if (C_PROG_EMPTY_TYPE == 2) begin
3664                if ((num_read_words == C_PROG_EMPTY_THRESH_ASSERT_VAL+1)
3665                    && RD_EN && !WR_EN) begin
3666                   prog_empty_d <= 1'b1;
3667                end else if ((num_read_words == C_PROG_EMPTY_THRESH_NEGATE_VAL)
3668                             && !RD_EN && WR_EN) begin
3669                   prog_empty_d <= 1'b0;
3670                end
3671
3672             //Single input threshold
3673             end else if (C_PROG_EMPTY_TYPE == 3) begin
3674                if ((num_read_words == PROG_EMPTY_THRESH+1)
3675                              && RD_EN && !WR_EN) begin
3676                   prog_empty_d <= 1'b1;
3677                end else if ((num_read_words == PROG_EMPTY_THRESH)
3678                              && !RD_EN && WR_EN) begin
3679                   prog_empty_d <= 1'b0;
3680                end else if (num_read_words <= PROG_EMPTY_THRESH) begin
3681                   prog_empty_d <= 1'b1;
3682                end else if (num_read_words > PROG_EMPTY_THRESH)begin
3683                   prog_empty_d <= 1'b0;
3684                end
3685
3686             //Dual input thresholds
3687             end else begin
3688                if (num_read_words <= PROG_EMPTY_THRESH_ASSERT) begin
3689                   prog_empty_d <= 1'b1;
3690                end else if ((num_read_words == PROG_EMPTY_THRESH_ASSERT+1)
3691                    && RD_EN && !WR_EN) begin
3692                   prog_empty_d <= 1'b1;
3693                end else if (num_read_words > PROG_EMPTY_THRESH_NEGATE)begin
3694                   prog_empty_d <= 1'b0;
3695                end else if ((num_read_words == PROG_EMPTY_THRESH_NEGATE)
3696                    && !RD_EN && WR_EN) begin
3697                   prog_empty_d <= 1'b0;
3698                end
3699             end
3700           end // (~ (C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0) )
3701
3702             //calculation for FWFT fifo
3703             if   (C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0)  begin
3704                //Single constant threshold
3705                if (C_PROG_EMPTY_TYPE == 1) begin
3706                   if ((num_read_words == C_PROG_EMPTY_THRESH_ASSERT_VAL+1 - 2)
3707                       && RD_EN && !WR_EN) begin
3708                      prog_empty_d <= 1'b1;
3709                   end else if ((num_read_words == C_PROG_EMPTY_THRESH_ASSERT_VAL - 2)
3710                                && WR_EN && !RD_EN) begin
3711                      prog_empty_d <= 1'b0;
3712                   end
3713                   //Dual constant thresholds
3714                end else if (C_PROG_EMPTY_TYPE == 2) begin
3715                   if ((num_read_words == C_PROG_EMPTY_THRESH_ASSERT_VAL+1 - 2)
3716                       && RD_EN && !WR_EN) begin
3717                      prog_empty_d <= 1'b1;
3718                   end else if ((num_read_words == C_PROG_EMPTY_THRESH_NEGATE_VAL - 2)
3719                                && !RD_EN && WR_EN) begin
3720                      prog_empty_d <= 1'b0;
3721                   end
3722
3723                   //Single input threshold
3724                end else if (C_PROG_EMPTY_TYPE == 3) begin
3725                   if ((num_read_words == PROG_EMPTY_THRESH+1 - 2)
3726                       && RD_EN && !WR_EN) begin
3727                      prog_empty_d <= 1'b1;
3728                   end else if ((num_read_words == PROG_EMPTY_THRESH - 2)
3729                                && !RD_EN && WR_EN) begin
3730                      prog_empty_d <= 1'b0;
3731                   end else if (num_read_words <= PROG_EMPTY_THRESH - 2) begin
3732                      prog_empty_d <= 1'b1;
3733                   end else if (num_read_words > PROG_EMPTY_THRESH - 2)begin
3734                      prog_empty_d <= 1'b0;
3735                   end
3736
3737                   //Dual input thresholds
3738                end else begin
3739                   if (num_read_words <= PROG_EMPTY_THRESH_ASSERT - 2) begin
3740                      prog_empty_d <= 1'b1;
3741                   end else if ((num_read_words == PROG_EMPTY_THRESH_ASSERT+1 - 2)
3742                                && RD_EN && !WR_EN) begin
3743                      prog_empty_d <= 1'b1;
3744                   end else if (num_read_words > PROG_EMPTY_THRESH_NEGATE - 2)begin
3745                      prog_empty_d <= 1'b0;
3746                   end else if ((num_read_words == PROG_EMPTY_THRESH_NEGATE - 2)
3747                                && !RD_EN && WR_EN) begin
3748                      prog_empty_d <= 1'b0;
3749                   end
3750                end
3751             end // (~ (C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0) )
3752
3753             ideal_prog_empty  <= prog_empty_d;
3754             if (rst_q && !rst_i) begin
3755                ideal_prog_full   <= 1'b0;
3756                prog_full_d       <= 1'b0;
3757             end else begin
3758                ideal_prog_full   <= prog_full_d;
3759             end
3760
3761          end //if (srst_i) begin
3762       end //if (rst_i) begin
3763    end //always @(posedge CLK or posedge rst_i) begin : gen_fifo_p
3764 endmodule // fifo_generator_v4_3_bhv_ver_ss
3765
3766
3767
3768 /**************************************************************************
3769  * First-Word Fall-Through module (preload 0)
3770  **************************************************************************/
3771 module fifo_generator_v4_3_bhv_ver_preload0
3772  (
3773   RD_CLK,
3774   RD_RST,
3775   RD_EN,
3776   FIFOEMPTY,
3777   FIFODATA,
3778   USERDATA,
3779   USERVALID,
3780   USERUNDERFLOW,
3781   USEREMPTY,
3782   USERALMOSTEMPTY,
3783   RAMVALID,
3784   FIFORDEN
3785   );
3786
3787  parameter  C_DOUT_RST_VAL            = "";
3788  parameter  C_DOUT_WIDTH              = 8;
3789  parameter  C_HAS_RST                 = 0;
3790  parameter  C_USE_DOUT_RST            = 0;
3791  parameter  C_USERVALID_LOW           = 0;
3792  parameter  C_USERUNDERFLOW_LOW       = 0;
3793
3794  //Inputs
3795  input                     RD_CLK;
3796  input                     RD_RST;
3797  input                     RD_EN;
3798  input                     FIFOEMPTY;
3799  input  [C_DOUT_WIDTH-1:0] FIFODATA;
3800
3801  //Outputs
3802  output [C_DOUT_WIDTH-1:0] USERDATA;
3803  output                    USERVALID;
3804  output                    USERUNDERFLOW;
3805  output                    USEREMPTY;
3806  output                    USERALMOSTEMPTY;
3807  output                    RAMVALID;
3808  output                    FIFORDEN;
3809
3810  //Inputs
3811  wire                      RD_CLK;
3812  wire                      RD_RST;
3813  wire                      RD_EN;
3814  wire                      FIFOEMPTY;
3815  wire [C_DOUT_WIDTH-1:0]   FIFODATA;
3816
3817  //Outputs
3818  reg [C_DOUT_WIDTH-1:0]    USERDATA;
3819  wire                      USERVALID;
3820  wire                      USERUNDERFLOW;
3821  wire                      USEREMPTY;
3822  wire                      USERALMOSTEMPTY;
3823  wire                      RAMVALID;
3824  wire                      FIFORDEN;
3825
3826  //Internal signals
3827  wire                      preloadstage1;
3828  wire                      preloadstage2;
3829  reg                       ram_valid_i;
3830  reg                       read_data_valid_i;
3831  wire                      ram_regout_en;
3832  wire                      ram_rd_en;
3833  reg                       empty_i        = 1'b1;
3834  reg                       empty_q        = 1'b1;
3835  reg                       rd_en_q        = 1'b0;
3836  reg                       almost_empty_i = 1'b1;
3837  reg                       almost_empty_q = 1'b1;
3838  wire                      rd_rst_i;
3839
3840
3841 /*************************************************************************
3842 * FUNCTIONS
3843 *************************************************************************/
3844
3845    /*************************************************************************
3846     * hexstr_conv
3847     *   Converts a string of type hex to a binary value (for C_DOUT_RST_VAL)
3848     ***********************************************************************/
3849     function [C_DOUT_WIDTH-1:0] hexstr_conv;
3850     input [(C_DOUT_WIDTH*8)-1:0] def_data;
3851
3852     integer index,i,j;
3853     reg [3:0] bin;
3854
3855     begin
3856       index = 0;
3857       hexstr_conv = 'b0;
3858       for( i=C_DOUT_WIDTH-1; i>=0; i=i-1 )
3859       begin
3860         case (def_data[7:0])
3861           8'b00000000 :
3862           begin
3863             bin = 4'b0000;
3864             i = -1;
3865           end
3866           8'b00110000 : bin = 4'b0000;
3867           8'b00110001 : bin = 4'b0001;
3868           8'b00110010 : bin = 4'b0010;
3869           8'b00110011 : bin = 4'b0011;
3870           8'b00110100 : bin = 4'b0100;
3871           8'b00110101 : bin = 4'b0101;
3872           8'b00110110 : bin = 4'b0110;
3873           8'b00110111 : bin = 4'b0111;
3874           8'b00111000 : bin = 4'b1000;
3875           8'b00111001 : bin = 4'b1001;
3876           8'b01000001 : bin = 4'b1010;
3877           8'b01000010 : bin = 4'b1011;
3878           8'b01000011 : bin = 4'b1100;
3879           8'b01000100 : bin = 4'b1101;
3880           8'b01000101 : bin = 4'b1110;
3881           8'b01000110 : bin = 4'b1111;
3882           8'b01100001 : bin = 4'b1010;
3883           8'b01100010 : bin = 4'b1011;
3884           8'b01100011 : bin = 4'b1100;
3885           8'b01100100 : bin = 4'b1101;
3886           8'b01100101 : bin = 4'b1110;
3887           8'b01100110 : bin = 4'b1111;
3888           default :
3889           begin
3890             bin = 4'bx;
3891           end
3892         endcase
3893         for( j=0; j<4; j=j+1)
3894         begin
3895           if ((index*4)+j < C_DOUT_WIDTH)
3896           begin
3897             hexstr_conv[(index*4)+j] = bin[j];
3898           end
3899         end
3900         index = index + 1;
3901         def_data = def_data >> 8;
3902       end
3903     end
3904   endfunction
3905
3906
3907    //*************************************************************************
3908    //  Set power-on states for regs
3909    //*************************************************************************
3910    initial begin
3911       ram_valid_i       = 1'b0;
3912       read_data_valid_i = 1'b0;
3913       USERDATA          = hexstr_conv(C_DOUT_RST_VAL);
3914    end //initial
3915
3916    //***************************************************************************
3917    //  connect up optional reset
3918    //***************************************************************************
3919    assign rd_rst_i = C_HAS_RST ? RD_RST : 0;
3920
3921
3922    //***************************************************************************
3923    //  preloadstage2 indicates that stage2 needs to be updated. This is true
3924    //  whenever read_data_valid is false, and RAM_valid is true.
3925    //***************************************************************************
3926    assign preloadstage2 = ram_valid_i & (~read_data_valid_i | RD_EN);
3927
3928    //***************************************************************************
3929    //  preloadstage1 indicates that stage1 needs to be updated. This is true
3930    //  whenever the RAM has data (RAM_EMPTY is false), and either RAM_Valid is
3931    //  false (indicating that Stage1 needs updating), or preloadstage2 is active
3932    //  (indicating that Stage2 is going to update, so Stage1, therefore, must
3933    //  also be updated to keep it valid.
3934    //***************************************************************************
3935    assign preloadstage1 = ((~ram_valid_i | preloadstage2) & ~FIFOEMPTY);
3936
3937    //***************************************************************************
3938    // Calculate RAM_REGOUT_EN
3939    //  The output registers are controlled by the ram_regout_en signal.
3940    //  These registers should be updated either when the output in Stage2 is
3941    //  invalid (preloadstage2), OR when the user is reading, in which case the
3942    //  Stage2 value will go invalid unless it is replenished.
3943    //***************************************************************************
3944    assign ram_regout_en = preloadstage2;
3945
3946    //***************************************************************************
3947    // Calculate RAM_RD_EN
3948    //   RAM_RD_EN will be asserted whenever the RAM needs to be read in order to
3949    //  update the value in Stage1.
3950    //   One case when this happens is when preloadstage1=true, which indicates
3951    //  that the data in Stage1 or Stage2 is invalid, and needs to automatically
3952    //  be updated.
3953    //   The other case is when the user is reading from the FIFO, which
3954    // guarantees that Stage1 or Stage2 will be invalid on the next clock
3955    // cycle, unless it is replinished by data from the memory. So, as long
3956    // as the RAM has data in it, a read of the RAM should occur.
3957    //***************************************************************************
3958    assign ram_rd_en = (RD_EN & ~FIFOEMPTY) | preloadstage1;
3959
3960    //***************************************************************************
3961    // Calculate RAMVALID_P0_OUT
3962    //   RAMVALID_P0_OUT indicates that the data in Stage1 is valid.
3963    //
3964    //   If the RAM is being read from on this clock cycle (ram_rd_en=1), then
3965    //   RAMVALID_P0_OUT is certainly going to be true.
3966    //   If the RAM is not being read from, but the output registers are being
3967    //   updated to fill Stage2 (ram_regout_en=1), then Stage1 will be emptying,
3968    //   therefore causing RAMVALID_P0_OUT to be false.
3969    //   Otherwise, RAMVALID_P0_OUT will remain unchanged.
3970    //***************************************************************************
3971    // PROCESS regout_valid
3972    always @ (posedge RD_CLK or posedge rd_rst_i) begin
3973       if (rd_rst_i) begin
3974          // asynchronous reset (active high)
3975          ram_valid_i     <= 1'b0;
3976       end else begin
3977          if (ram_rd_en == 1'b1) begin
3978             ram_valid_i   <= 1'b1;
3979          end else begin
3980             if (ram_regout_en == 1'b1)
3981               ram_valid_i <= 1'b0;
3982             else
3983               ram_valid_i <= ram_valid_i;
3984          end
3985       end //rd_rst_i
3986    end //always
3987
3988    //***************************************************************************
3989    // Calculate READ_DATA_VALID
3990    //  READ_DATA_VALID indicates whether the value in Stage2 is valid or not.
3991    //  Stage2 has valid data whenever Stage1 had valid data and
3992    //  ram_regout_en_i=1, such that the data in Stage1 is propogated
3993    //  into Stage2.
3994    //***************************************************************************
3995    always @ (posedge RD_CLK or posedge rd_rst_i) begin
3996       if (rd_rst_i)
3997         read_data_valid_i <= 1'b0;
3998       else
3999         read_data_valid_i <= ram_valid_i | (read_data_valid_i & ~RD_EN);
4000    end //always
4001
4002
4003    //**************************************************************************
4004    // Calculate EMPTY
4005    //  Defined as the inverse of READ_DATA_VALID
4006    //
4007    // Description:
4008    //
4009    //  If read_data_valid_i indicates that the output is not valid,
4010    // and there is no valid data on the output of the ram to preload it
4011    // with, then we will report empty.
4012    //
4013    //  If there is no valid data on the output of the ram and we are
4014    // reading, then the FIFO will go empty.
4015    //
4016    //**************************************************************************
4017    always @ (posedge RD_CLK or posedge rd_rst_i) begin
4018       if (rd_rst_i) begin
4019          // asynchronous reset (active high)
4020          empty_i <= 1'b1;
4021          empty_q <= 1'b1;
4022       end else begin
4023          // rising clock edge
4024          empty_i <= (~ram_valid_i & ~read_data_valid_i) | (~ram_valid_i & RD_EN);
4025          empty_q <= empty_i;
4026       end
4027    end //always
4028
4029    //Register RD_EN from user to calculate USERUNDERFLOW.
4030    always @ (posedge RD_CLK or posedge rd_rst_i) begin
4031       if (rd_rst_i) begin
4032          // asynchronous reset (active high)
4033          rd_en_q <= 1'b0;
4034       end else begin
4035          // rising clock edge
4036          rd_en_q <= RD_EN;
4037       end
4038    end //always
4039
4040
4041    //***************************************************************************
4042    // Calculate user_almost_empty
4043    //  user_almost_empty is defined such that, unless more words are written
4044    //  to the FIFO, the next read will cause the FIFO to go EMPTY.
4045    //
4046    //  In most cases, whenever the output registers are updated (due to a user
4047    // read or a preload condition), then user_almost_empty will update to
4048    // whatever RAM_EMPTY is.
4049    //
4050    //  The exception is when the output is valid, the user is not reading, and
4051    // Stage1 is not empty. In this condition, Stage1 will be preloaded from the
4052    // memory, so we need to make sure user_almost_empty deasserts properly under
4053    // this condition.
4054    //***************************************************************************
4055    always @ (posedge RD_CLK or posedge rd_rst_i)
4056      begin
4057         if (rd_rst_i)                // asynchronous reset (active high)
4058           begin
4059              almost_empty_i <= 1'b1;
4060              almost_empty_q <= 1'b1;
4061           end
4062         else // rising clock edge
4063           begin
4064              if ((ram_regout_en) | (~FIFOEMPTY & read_data_valid_i & ~RD_EN))
4065                begin
4066                   almost_empty_i <= FIFOEMPTY;
4067                end
4068              almost_empty_q   <= empty_i;
4069           end
4070      end //always
4071
4072
4073    assign USEREMPTY       = empty_i;
4074    assign USERALMOSTEMPTY = almost_empty_i;
4075    assign FIFORDEN        = ram_rd_en;
4076    assign RAMVALID        = ram_valid_i;
4077    assign USERVALID       = C_USERVALID_LOW ? ~read_data_valid_i : read_data_valid_i;
4078    assign USERUNDERFLOW   = C_USERUNDERFLOW_LOW ? ~(empty_q & rd_en_q) : empty_q & rd_en_q;
4079
4080    always @ (posedge RD_CLK or posedge rd_rst_i)
4081      begin
4082         if (rd_rst_i && C_USE_DOUT_RST == 1)  //asynchronous reset (active high)
4083           USERDATA   <= hexstr_conv(C_DOUT_RST_VAL);
4084         else  // rising clock edge
4085           if (ram_regout_en)
4086             USERDATA <= FIFODATA;
4087      end //always
4088
4089
4090
4091
4092
4093 endmodule