2 //************************************************************************
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3 //************************************************************************
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4 //** This model is the property of Cypress Semiconductor Corp and is **
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5 //** protected by the US copyright laws, any unauthorized copying and **
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6 //** distribution is prohibited. Cypress reserves the right to change **
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7 //** any of the functional specifications without any prior notice. **
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8 //** Cypress is not liable for any damages which may result from the **
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9 //** use of this functional model. **
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11 //** File Name : CY7C1356 **
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13 //** Revision : 1.0 - 08/03/2004 **
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15 //** The timings are to be selected by the user depending upon the **
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16 //** frequency of operation from the datasheet. **
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18 //** Model : CY7C1356C - NoBL Pipelined SRAM **
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19 //** Queries : MPD Applications **
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20 //** Website: www.cypress.com/support **
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21 //************************************************************************
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22 //************************************************************************
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24 `timescale 1ns / 10ps
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26 // NOTE : Any setup/hold errors will force input signal to x state
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27 // or if results indeterminant (write addr) core is reset x
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29 // define fixed values
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31 `define wordsize (18 -1) //
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32 `define no_words (1048576 -1) // 1M x 18 RAM
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34 module cy1356 ( d, clk, a, bws, we_b, adv_lb, ce1b, ce2, ce3b, oeb, cenb, mode);
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36 inout [`wordsize:0] d;
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37 input clk, // clock input (R)
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38 we_b, // byte write enable(L)
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39 adv_lb, // burst(H)/load(L) address
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40 ce1b, // chip enable(L)
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41 ce2, // chip enable(H)
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42 ce3b, // chip enable(L)
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43 oeb, // async output enable(L)(read)
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44 cenb, // clock enable(L)
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45 mode; // interleave(H)/linear(L) burst
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46 input [1:0] bws; // byte write select(L)
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47 input [18:0] a; // address bus
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49 // *** NOTE DEVICE OPERATES #0.01 AFTER CLOCK ***
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50 // *** THEREFORE DELAYS HAVE TO TAKE THIS INTO ACCOUNT ***
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53 //**********************************************************************
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54 // Timings for 225MHz
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55 //**********************************************************************
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67 //***********************************************************************
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68 // Timings for 200MHz
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69 //**********************************************************************
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82 //***********************************************************************
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84 //**********************************************************************
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85 // This model is configured for 166 MHz Operation (CY7C1356-166).
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86 //**********************************************************************
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100 reg notifier; // error support reg's
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111 wire chipen; // combined chip enable (high for an active chip)
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113 reg chipen_d; // _d = delayed
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114 reg chipen_o; // _o = operational = delayed sig or _d sig
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116 wire writestate; // holds 1 if any of writebus is low
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120 wire loadcyc; // holds 1 for load cycles (setup and hold checks)
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121 wire writecyc; // holds 1 for write cycles (setup and hold checks)
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122 wire [1:0] bws; // holds the bws values
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124 wire [1:0] writebusb; // holds the "internal" bws bus based on we_b
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125 reg [1:0] writebusb_d;
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126 reg [1:0] writebusb_o;
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128 wire [2:0] operation; // holds chipen, adv_ld and writestate
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129 reg [2:0] operation_d;
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130 reg [2:0] operation_o;
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132 wire [18:0] a; // address input bus
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136 reg [`wordsize:0] do; // data output reg
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137 reg [`wordsize:0] di; // data input bus
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138 reg [`wordsize:0] dd; // data delayed bus
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140 wire tristate; // tristate output (on a bytewise basis) when asserted
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141 reg cetri; // register set by chip disable which sets the tristate
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142 reg oetri; // register set by oe which sets the tristate
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143 reg enable; // register to make the ram enabled when equal to 1
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144 reg [18:0] addreg; // register to hold the input address
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145 reg [`wordsize:0] pipereg; // register for the output data
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147 reg [`wordsize:0] mem [0:`no_words]; // RAM array
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149 reg [`wordsize:0] writeword; // temporary holding register for the write data
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150 reg burstinit; // register to hold a[0] for burst type
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151 reg [18:0] i; // temporary register used to write to all mem locs.
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152 reg writetri; // tristate
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153 reg lw, bw; // pipelined write functions
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157 wire [`wordsize:0] d = !tristate ? do[`wordsize:0] : 18'bz ; // data bus
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159 assign chipen = (adv_lb == 1 ) ? chipen_d :
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160 ~ce1b & ce2 & ~ce3b ;
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162 assign writestate = ~& writebusb;
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164 assign operation = {chipen, adv_lb, writestate};
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166 assign writebusb[1:0] = ( we_b ==0 & adv_lb ==0) ? bws[1:0]:
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167 ( we_b ==1 & adv_lb ==0) ? 2'b11 :
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168 ( we_bl ==0 & adv_lb ==1) ? bws[1:0]:
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169 ( we_bl ==1 & adv_lb ==1) ? 2'b11 :
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172 assign loadcyc = chipen & !cenb;
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174 assign writecyc = writestate_d & enable & ~cenb & chipen; // check
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176 assign tristate = cetri | writetri | oetri;
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180 // formers for notices/errors etc
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182 //$display("NOTICE : xxx :");
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183 //$display("WARNING : xxx :");
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184 //$display("ERROR *** : xxx :");
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187 // initialize the output to be tri-state, ram to be disabled
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225 // *** SETUP / HOLD VIOLATIONS ***
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229 $display("NOTICE : 020 : Data bus corruption");
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237 $display("NOTICE : 010 : Byte write corruption");
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245 $display("NOTICE : 011 : Byte enable corruption");
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253 $display("NOTICE : 012 : CE1B corruption");
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261 $display("NOTICE : 013 : CE2 corruption");
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269 $display("NOTICE : 014 : CE3B corruption");
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277 $display("NOTICE : 015 : CENB corruption");
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285 $display("NOTICE : 016 : ADV_LB corruption");
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286 force adv_lb = 1'bx;
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291 // synchronous functions from clk edge
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293 always @(posedge clk)
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297 // latch conditions on adv_lb
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304 chipen_d <= chipen;
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307 chipen_o <= chipen;
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308 writestate_o <= writestate;
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309 writestate_d <= writestate_o;
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310 writebusb_o <= writebusb;
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311 writebusb_d <= writebusb_o;
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312 operation_o <= operation;
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317 // execute previously pipelined fns
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329 // decode input/piplined state
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331 casex (operation_o)
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336 3'b110 : burstread;
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337 default : unknown; // output unknown values and display an error message
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340 do <= `tco pipereg;
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344 // *** task section ***
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348 if (enable) cetri <= `tclz 0;
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349 writetri <= `tchz 0;
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351 pipereg = mem[addreg];
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357 if (enable) cetri <= `tclz 0;
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358 writeword = mem[addreg]; // set up a word to hold the data for the current location
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359 /* overwrite the current word for the bytes being written to */
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360 if (!writebusb_d[1]) writeword[17:9] = di[17:9];
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361 if (!writebusb_d[0]) writeword[8:0] = di[8:0];
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362 writeword = writeword & writeword; //convert z to x states
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363 mem[addreg] = writeword; // store the new word into the memory location
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364 //writetri <= `tchz 1; // tristate the outputs
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371 writetri <= `tchz 1; // tristate the outputs
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378 writetri <= `tchz 1; // tristate the outputs
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384 burstinit = a_o[0];
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393 burstinit = a_d[0];
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417 // $display ("Unknown function: Operation = %b\n", operation);
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431 if (burstinit == 0 || mode == 0)
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434 2'b00: addreg[1:0] = 2'b01;
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435 2'b01: addreg[1:0] = 2'b10;
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436 2'b10: addreg[1:0] = 2'b11;
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437 2'b11: addreg[1:0] = 2'b00;
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438 default: addreg[1:0] = 2'bxx;
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444 2'b00: addreg[1:0] = 2'b11;
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445 2'b01: addreg[1:0] = 2'b00;
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446 2'b10: addreg[1:0] = 2'b01;
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447 2'b11: addreg[1:0] = 2'b10;
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448 default: addreg[1:0] = 2'bxx;
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457 // specify the setup and hold checks
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459 // notifier will wipe memory as result is indeterminent
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461 $setuphold(posedge clk &&& loadcyc, a, `tas, `tah, notifier);
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463 // noti1 should make ip = 'bx;
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465 $setuphold(posedge clk, bws, `tas, `tah, noti1_0);
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467 $setuphold(posedge clk, we_b, `tas, `tah, noti1_1);
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468 $setuphold(posedge clk, ce1b, `tas, `tah, noti1_2);
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469 $setuphold(posedge clk, ce2, `tas, `tah, noti1_3);
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470 $setuphold(posedge clk, ce3b, `tas, `tah, noti1_4);
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472 // noti2 should make d = 18'hxxxxx;
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474 $setuphold(posedge clk &&& writecyc, d, `tas, `tah, noti2);
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476 // add extra tests here.
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478 $setuphold(posedge clk, cenb, `tas, `tah, noti1_5);
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479 $setuphold(posedge clk, adv_lb, `tas, `tah, noti1_6);
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