8 output [31:0] Tx_mac_data,
9 output [1:0] Tx_mac_BE,
13 // To buffer interface
14 input [31:0] rd_dat_i,
24 input [31:0] set_data,
27 input [15:0] rx_fifo_status,
29 //input [7:0] tx_channel,
30 //input [7:0] tx_flags
35 wire [7:0] tx_channel;
37 header_ram #(.REGNUM(32),.WIDTH(32)) tx_header_ram
38 (.clk(clk),.set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
39 .addr(hdr_adr),.q(hdr_dat));
41 setting_reg #(.my_addr(32)) sr_channel
42 (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),.in(set_data),
43 .out(tx_channel),.changed());
45 // Might as well use a shortfifo here since they are basically free
46 wire empty, full, sfifo_write, sfifo_read;
47 wire [33:0] sfifo_in, sfifo_out;
49 shortfifo #(.WIDTH(34)) txmac_sfifo
50 (.clk(clk),.rst(rst),.clear(0),
51 .datain(sfifo_in),.write(sfifo_write),.full(full),
52 .dataout(sfifo_out),.read(sfifo_read),.empty(empty));
55 // Inputs -- Tx_mac_wa, sfifo_out, empty
56 // outputs -- sfifo_read, Tx_mac_data, Tx_mac_wr, Tx_mac_BE, Tx_mac_sop, Tx_mac_eop
58 // We are allowed to do one more write after we are told the FIFO is full
59 // This allows us to register the _wa signal and speed up timing.
62 tx_mac_wa_d1 <= Tx_mac_wa;
65 localparam PROT_IDLE = 0;
66 localparam PROT_HDR1 = 1;
67 localparam PROT_HDR2 = 2;
68 localparam PROT_HDR3 = 3;
69 localparam PROT_HDR4 = 4;
70 localparam PROT_HDR5 = 5;
71 localparam PROT_PKT = 6;
78 else if(set_stb & (set_addr == 36))
79 tx_seqnum <= set_data[7:0];
80 else if(tx_mac_wa_d1 & all_match & (prot_state == PROT_HDR5))
81 tx_seqnum <= tx_seqnum + 1;
85 prot_state <= PROT_IDLE;
87 if(tx_mac_wa_d1 & ~empty)
90 prot_state <= PROT_HDR1;
92 prot_state <= PROT_HDR2;
94 prot_state <= PROT_HDR3;
96 prot_state <= PROT_HDR4;
98 prot_state <= PROT_HDR5;
100 prot_state <= PROT_PKT;
102 if(sfifo_out[32] & ~empty)
103 prot_state <= PROT_IDLE;
105 prot_state <= PROT_IDLE;
106 endcase // case(prot_state)
108 assign hdr_adr = {1'b0,prot_state};
109 wire match = (hdr_dat == sfifo_out[31:0]);
110 always @(posedge clk)
111 if(prot_state == PROT_IDLE)
113 else if(tx_mac_wa_d1 & ~empty &
114 ((prot_state==PROT_HDR1)|(prot_state==PROT_HDR2)|(prot_state==PROT_HDR3)))
115 all_match <= all_match & match;
117 localparam ETH_TYPE = 16'hBEEF;
119 ((prot_state == PROT_HDR5) & all_match) ? {rx_fifo_status,tx_seqnum,rx_seqnum} :
121 assign sfifo_read = (prot_state != PROT_IDLE) & ~empty & tx_mac_wa_d1;
122 assign Tx_mac_wr = sfifo_read;
123 assign Tx_mac_BE = 0; // Since we only deal with packets that are multiples of 32 bits long
124 assign Tx_mac_sop = sfifo_out[33];
125 assign Tx_mac_eop = sfifo_out[32];
127 // BUFFER side signals
129 always @(posedge clk)
132 else if(rd_eop_i & ~full)
137 assign sfifo_in = {rd_sop_i, rd_eop_i, rd_dat_i};
138 assign sfifo_write = xfer_active & ~full;
140 assign rd_read_o = sfifo_write;
141 assign rd_done_o = 0; // Always send everything we're given?
142 assign rd_error_o = 0; // No possible error situations?
144 endmodule // tx_prot_engine