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   1 //////////////////////////////////////////////////////////////////////\r
   2 ////                                                              ////\r
   3 ////  eth_clk_div2.v                                              ////\r
   4 ////                                                              ////\r
   5 ////  This file is part of the Ethernet IP core project           ////\r
   6 ////  http://www.opencores.org/projects.cgi/web/ethernet_tri_mode/////\r
   7 ////                                                              ////\r
   8 ////  Author(s):                                                  ////\r
   9 ////      - Jon Gao (gaojon@yahoo.com)                            ////\r
  10 ////                                                              ////\r
  11 ////                                                              ////\r
  12 //////////////////////////////////////////////////////////////////////\r
  13 ////                                                              ////\r
  14 //// Copyright (C) 2001 Authors                                   ////\r
  15 ////                                                              ////\r
  16 //// This source file may be used and distributed without         ////\r
  17 //// restriction provided that this copyright statement is not    ////\r
  18 //// removed from the file and that any derivative work contains  ////\r
  19 //// the original copyright notice and the associated disclaimer. ////\r
  20 ////                                                              ////\r
  21 //// This source file is free software; you can redistribute it   ////\r
  22 //// and/or modify it under the terms of the GNU Lesser General   ////\r
  23 //// Public License as published by the Free Software Foundation; ////\r
  24 //// either version 2.1 of the License, or (at your option) any   ////\r
  25 //// later version.                                               ////\r
  26 ////                                                              ////\r
  27 //// This source is distributed in the hope that it will be       ////\r
  28 //// useful, but WITHOUT ANY WARRANTY; without even the implied   ////\r
  29 //// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////\r
  30 //// PURPOSE.  See the GNU Lesser General Public License for more ////\r
  31 //// details.                                                     ////\r
  32 ////                                                              ////\r
  33 //// You should have received a copy of the GNU Lesser General    ////\r
  34 //// Public License along with this source; if not, download it   ////\r
  35 //// from http://www.opencores.org/lgpl.shtml                     ////\r
  36 ////                                                              ////\r
  37 //////////////////////////////////////////////////////////////////////\r
  38 //                                                                    \r
  39 // CVS Revision History                                               \r
  40 //                                                                    \r
  41 // $Log: CLK_DIV2.v,v $\r
  42 // Revision 1.3  2006/01/19 14:07:56  maverickist\r
  43 // verification is complete.\r
  44 //\r
  45 // Revision 1.2  2005/12/16 06:44:20  Administrator\r
  46 // replaced tab with space.\r
  47 // passed 9.6k length frame test.\r
  48 //\r
  49 // Revision 1.1.1.1  2005/12/13 01:51:44  Administrator\r
  50 // no message\r
  51 // \r
  52 \r
  53 \r
  54 //////////////////////////////////////////////////////////////////////\r
  55 // This file can only used for simulation .\r
  56 // You need to replace it with your own element according to technology\r
  57 //////////////////////////////////////////////////////////////////////\r
  58 \r
  59 module eth_clk_div2 (\r
  60   input       Reset,\r
  61   input       IN,\r
  62   output  reg OUT\r
  63 );\r
  64 \r
  65 always @ (posedge IN or posedge Reset)\r
  66   if (Reset)\r
  67     OUT <= 0;\r
  68   else\r
  69     OUT <= ~OUT;\r
  70     \r
  71 endmodule\r