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   1 //////////////////////////////////////////////////////////////////////\r
   2 ////                                                              ////\r
   3 ////  RMON_ctrl.v                                                 ////\r
   4 ////                                                              ////\r
   5 ////  This file is part of the Ethernet IP core project           ////\r
   6 ////  http://www.opencores.org/projects.cgi/web/ethernet_tri_mode/////\r
   7 ////                                                              ////\r
   8 ////  Author(s):                                                  ////\r
   9 ////      - Jon Gao (gaojon@yahoo.com)                            ////\r
  10 ////                                                              ////\r
  11 ////                                                              ////\r
  12 //////////////////////////////////////////////////////////////////////\r
  13 ////                                                              ////\r
  14 //// Copyright (C) 2001 Authors                                   ////\r
  15 ////                                                              ////\r
  16 //// This source file may be used and distributed without         ////\r
  17 //// restriction provided that this copyright statement is not    ////\r
  18 //// removed from the file and that any derivative work contains  ////\r
  19 //// the original copyright notice and the associated disclaimer. ////\r
  20 ////                                                              ////\r
  21 //// This source file is free software; you can redistribute it   ////\r
  22 //// and/or modify it under the terms of the GNU Lesser General   ////\r
  23 //// Public License as published by the Free Software Foundation; ////\r
  24 //// either version 2.1 of the License, or (at your option) any   ////\r
  25 //// later version.                                               ////\r
  26 ////                                                              ////\r
  27 //// This source is distributed in the hope that it will be       ////\r
  28 //// useful, but WITHOUT ANY WARRANTY; without even the implied   ////\r
  29 //// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////\r
  30 //// PURPOSE.  See the GNU Lesser General Public License for more ////\r
  31 //// details.                                                     ////\r
  32 ////                                                              ////\r
  33 //// You should have received a copy of the GNU Lesser General    ////\r
  34 //// Public License along with this source; if not, download it   ////\r
  35 //// from http://www.opencores.org/lgpl.shtml                     ////\r
  36 ////                                                              ////\r
  37 //////////////////////////////////////////////////////////////////////\r
  38 //                                                                    \r
  39 // CVS Revision History                                               \r
  40 //                                                                    \r
  41 // $Log: RMON_ctrl.v,v $\r
  42 // Revision 1.4  2006/06/25 04:58:57  maverickist\r
  43 // no message\r
  44 //\r
  45 // Revision 1.3  2006/01/19 14:07:55  maverickist\r
  46 // verification is complete.\r
  47 //\r
  48 // Revision 1.2  2005/12/16 06:44:19  Administrator\r
  49 // replaced tab with space.\r
  50 // passed 9.6k length frame test.\r
  51 //\r
  52 // Revision 1.1.1.1  2005/12/13 01:51:45  Administrator\r
  53 // no message\r
  54 //  \r
  55 module RMON_ctrl (\r
  56 Clk             ,      \r
  57 Reset           ,      \r
  58 //RMON_ctrl        \r
  59 Reg_apply_0     ,      \r
  60 Reg_addr_0      ,      \r
  61 Reg_data_0      ,      \r
  62 Reg_next_0      ,      \r
  63 Reg_apply_1     ,      \r
  64 Reg_addr_1      ,      \r
  65 Reg_data_1      ,      \r
  66 Reg_next_1      ,      \r
  67 //dual-port ram\r
  68 Addra               ,  \r
  69 Dina                ,  \r
  70 Douta               ,  \r
  71 Wea                 ,  \r
  72 //CPU                  \r
  73 CPU_rd_addr     ,  \r
  74 CPU_rd_apply        ,  \r
  75 CPU_rd_grant        ,\r
  76 CPU_rd_dout\r
  77 \r
  78 );\r
  79 input           Clk             ;\r
  80 input           Reset           ;\r
  81                 //RMON_ctrl\r
  82 input           Reg_apply_0     ;\r
  83 input   [4:0]   Reg_addr_0      ;\r
  84 input   [15:0]  Reg_data_0      ;\r
  85 output          Reg_next_0      ;\r
  86 input           Reg_apply_1     ;\r
  87 input   [4:0]   Reg_addr_1      ;\r
  88 input   [15:0]  Reg_data_1      ;\r
  89 output          Reg_next_1      ;\r
  90                 //dual-port ram \r
  91                 //port-a for Rmon  \r
  92 output  [5:0]   Addra               ;\r
  93 output  [31:0]  Dina                ;\r
  94 input   [31:0]  Douta               ;\r
  95 output          Wea                 ;\r
  96                 //CPU\r
  97 input   [5:0]   CPU_rd_addr         ;\r
  98 input           CPU_rd_apply        ;\r
  99 output          CPU_rd_grant        ;\r
 100 output  [31:0]  CPU_rd_dout         ;\r
 101 \r
 102 \r
 103 \r
 104 \r
 105 //******************************************************************************\r
 106 //internal signals                                                              \r
 107 //******************************************************************************\r
 108 \r
 109 parameter       StateCPU        =4'd00;\r
 110 parameter       StateMAC0       =4'd01;\r
 111 parameter       StateMAC1       =4'd02;\r
 112 \r
 113 \r
 114 reg [3:0]       CurrentState /* synthesys syn_keep=1 */;\r
 115 reg [3:0]       NextState;\r
 116 reg [3:0]       CurrentState_reg;\r
 117 \r
 118 reg [4:0]       StepCounter;\r
 119 reg [5:0]       Addra               ;\r
 120 reg [31:0]      Dina;\r
 121 reg             Reg_next_0      ;\r
 122 reg             Reg_next_1      ;\r
 123 reg             Write;\r
 124 reg             Read;\r
 125 reg             Pipeline;\r
 126 reg [31:0]      CPU_rd_dout         ;\r
 127 reg             CPU_rd_apply_reg    ;\r
 128 //******************************************************************************\r
 129 //State Machine                                                            \r
 130 //******************************************************************************\r
 131 \r
 132 always @(posedge Clk or posedge Reset)\r
 133     if (Reset)\r
 134         CurrentState    <=StateMAC0;\r
 135     else\r
 136         CurrentState    <=NextState;\r
 137         \r
 138 always @(posedge Clk or posedge Reset)\r
 139     if (Reset)  \r
 140         CurrentState_reg    <=StateMAC0;\r
 141     else if(CurrentState!=StateCPU)\r
 142         CurrentState_reg    <=CurrentState;\r
 143                 \r
 144 always @(CurrentState or CPU_rd_apply_reg or Reg_apply_0 or CurrentState_reg\r
 145                                        or Reg_apply_1   \r
 146                                        or StepCounter\r
 147                                        )\r
 148     case(CurrentState)\r
 149         StateMAC0:\r
 150             if(!Reg_apply_0&&CPU_rd_apply_reg)\r
 151                 NextState   =StateCPU;\r
 152             else if(!Reg_apply_0)\r
 153                 NextState   =StateMAC1;\r
 154             else\r
 155                 NextState   =CurrentState;\r
 156         StateMAC1:\r
 157             if(!Reg_apply_1&&CPU_rd_apply_reg)\r
 158                 NextState   =StateCPU;\r
 159             else if(!Reg_apply_1)\r
 160                 NextState   =StateMAC0;\r
 161             else\r
 162                 NextState   =CurrentState;\r
 163         StateCPU:\r
 164             if (StepCounter==3)\r
 165                 case (CurrentState_reg)\r
 166                     StateMAC0   :NextState  =StateMAC0 ;\r
 167                     StateMAC1   :NextState  =StateMAC1 ;\r
 168                     default     :NextState  =StateMAC0;\r
 169                 endcase\r
 170             else\r
 171                 NextState   =CurrentState;\r
 172             \r
 173         default:\r
 174                 NextState   =StateMAC0;\r
 175     endcase\r
 176                 \r
 177 \r
 178 \r
 179 always @(posedge Clk or posedge Reset)\r
 180     if (Reset)\r
 181         StepCounter     <=0;\r
 182     else if(NextState!=CurrentState)\r
 183         StepCounter     <=0;\r
 184     else if (StepCounter!=4'hf)\r
 185         StepCounter     <=StepCounter + 1;\r
 186 \r
 187 //******************************************************************************\r
 188 //temp signals                                                            \r
 189 //******************************************************************************\r
 190 always @(StepCounter)\r
 191     if( StepCounter==1||StepCounter==4||\r
 192         StepCounter==7||StepCounter==10)\r
 193         Read    =1;\r
 194     else\r
 195         Read    =0;\r
 196 \r
 197 always @(StepCounter or CurrentState)\r
 198     if( StepCounter==2||StepCounter==5||\r
 199         StepCounter==8||StepCounter==11)\r
 200         Pipeline    =1;\r
 201     else\r
 202         Pipeline    =0;\r
 203                 \r
 204 always @(StepCounter or CurrentState)\r
 205     if( StepCounter==3||StepCounter==6||\r
 206         StepCounter==9||StepCounter==12)\r
 207         Write   =1;\r
 208     else\r
 209         Write   =0;\r
 210         \r
 211         \r
 212 //******************************************************************************\r
 213 //gen output signals                                                        \r
 214 //******************************************************************************    \r
 215 //Addra \r
 216 always @(*)\r
 217     case(CurrentState)\r
 218         StateMAC0 :     Addra={1'd0 ,Reg_addr_0 };\r
 219         StateMAC1 :     Addra={1'd1 ,Reg_addr_1 };\r
 220         StateCPU:       Addra=CPU_rd_addr;\r
 221         default:        Addra=0;\r
 222         endcase\r
 223     \r
 224 //Dina\r
 225 always @(posedge Clk or posedge Reset)\r
 226     if (Reset)\r
 227         Dina    <=0;\r
 228     else \r
 229         case(CurrentState)\r
 230             StateMAC0 :     Dina<=Douta+Reg_data_0 ;\r
 231             StateMAC1 :     Dina<=Douta+Reg_data_1 ;\r
 232             StateCPU:       Dina<=0;\r
 233             default:        Dina<=0;\r
 234         endcase\r
 235     \r
 236 assign  Wea     =Write;\r
 237 //Reg_next\r
 238 always @(CurrentState or Pipeline)\r
 239     if(CurrentState==StateMAC0)\r
 240         Reg_next_0  =Pipeline;\r
 241     else\r
 242         Reg_next_0  =0;\r
 243     \r
 244 always @(CurrentState or Pipeline)\r
 245     if(CurrentState==StateMAC1)\r
 246         Reg_next_1  =Pipeline;\r
 247     else\r
 248         Reg_next_1  =0;     \r
 249 \r
 250 \r
 251 //CPU_rd_grant   \r
 252 reg     CPU_rd_apply_dl1;\r
 253 reg     CPU_rd_apply_dl2;\r
 254 //rising edge\r
 255 always @ (posedge Clk or posedge Reset)\r
 256     if (Reset)\r
 257         begin\r
 258         CPU_rd_apply_dl1        <=0;\r
 259         CPU_rd_apply_dl2        <=0;\r
 260         end\r
 261     else\r
 262         begin\r
 263         CPU_rd_apply_dl1        <=CPU_rd_apply;\r
 264         CPU_rd_apply_dl2        <=CPU_rd_apply_dl1;\r
 265         end     \r
 266 \r
 267 always @ (posedge Clk or posedge Reset)\r
 268     if (Reset)\r
 269         CPU_rd_apply_reg    <=0;\r
 270     else if (CPU_rd_apply_dl1&!CPU_rd_apply_dl2)\r
 271         CPU_rd_apply_reg    <=1;\r
 272     else if (CurrentState==StateCPU&&Write)\r
 273         CPU_rd_apply_reg    <=0;\r
 274 \r
 275 assign CPU_rd_grant = CPU_rd_apply & CPU_rd_apply_dl1 & CPU_rd_apply_dl2 & !CPU_rd_apply_reg;\r
 276 \r
 277 always @ (posedge Clk or posedge Reset)\r
 278     if (Reset)\r
 279         CPU_rd_dout     <=0;\r
 280     else if (Pipeline&&CurrentState==StateCPU)\r
 281         CPU_rd_dout     <=Douta;        \r
 282 \r
 283 endmodule           \r