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   1 //////////////////////////////////////////////////////////////////////\r
   2 ////                                                              ////\r
   3 ////  Random_gen.v                                                ////\r
   4 ////                                                              ////\r
   5 ////  This file is part of the Ethernet IP core project           ////\r
   6 ////  http://www.opencores.org/projects.cgi/web/ethernet_tri_mode/////\r
   7 ////                                                              ////\r
   8 ////  Author(s):                                                  ////\r
   9 ////      - Jon Gao (gaojon@yahoo.com)                            ////\r
  10 ////                                                              ////\r
  11 ////                                                              ////\r
  12 //////////////////////////////////////////////////////////////////////\r
  13 ////                                                              ////\r
  14 //// Copyright (C) 2001 Authors                                   ////\r
  15 ////                                                              ////\r
  16 //// This source file may be used and distributed without         ////\r
  17 //// restriction provided that this copyright statement is not    ////\r
  18 //// removed from the file and that any derivative work contains  ////\r
  19 //// the original copyright notice and the associated disclaimer. ////\r
  20 ////                                                              ////\r
  21 //// This source file is free software; you can redistribute it   ////\r
  22 //// and/or modify it under the terms of the GNU Lesser General   ////\r
  23 //// Public License as published by the Free Software Foundation; ////\r
  24 //// either version 2.1 of the License, or (at your option) any   ////\r
  25 //// later version.                                               ////\r
  26 ////                                                              ////\r
  27 //// This source is distributed in the hope that it will be       ////\r
  28 //// useful, but WITHOUT ANY WARRANTY; without even the implied   ////\r
  29 //// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////\r
  30 //// PURPOSE.  See the GNU Lesser General Public License for more ////\r
  31 //// details.                                                     ////\r
  32 ////                                                              ////\r
  33 //// You should have received a copy of the GNU Lesser General    ////\r
  34 //// Public License along with this source; if not, download it   ////\r
  35 //// from http://www.opencores.org/lgpl.shtml                     ////\r
  36 ////                                                              ////\r
  37 //////////////////////////////////////////////////////////////////////\r
  38 \r
  39 module Random_gen( \r
  40 Reset           ,\r
  41 Clk             ,\r
  42 Init            ,\r
  43 RetryCnt        ,\r
  44 Random_time_meet\r
  45 );\r
  46 input           Reset           ;\r
  47 input           Clk             ;\r
  48 input           Init            ;\r
  49 input   [3:0]   RetryCnt        ;\r
  50 output          Random_time_meet;   \r
  51 \r
  52 //******************************************************************************\r
  53 //internal signals                                                              \r
  54 //******************************************************************************\r
  55 reg [9:0]       Random_sequence ;\r
  56 reg [9:0]       Random          ;\r
  57 reg [9:0]       Random_counter  ;\r
  58 reg [7:0]       Slot_time_counter; //256*2=512bit=1 slot time\r
  59 reg             Random_time_meet;\r
  60 \r
  61 //******************************************************************************\r
  62 always @ (posedge Clk or posedge Reset)\r
  63     if (Reset)\r
  64         Random_sequence     <=0;\r
  65     else\r
  66         Random_sequence     <={Random_sequence[8:0],~(Random_sequence[2]^Random_sequence[9])};\r
  67         \r
  68 always @ (RetryCnt or Random_sequence)\r
  69     case (RetryCnt)\r
  70         4'h0    :   Random={9'b0,Random_sequence[0]};\r
  71         4'h1    :   Random={8'b0,Random_sequence[1:0]};     \r
  72         4'h2    :   Random={7'b0,Random_sequence[2:0]};\r
  73         4'h3    :   Random={6'b0,Random_sequence[3:0]};\r
  74         4'h4    :   Random={5'b0,Random_sequence[4:0]};\r
  75         4'h5    :   Random={4'b0,Random_sequence[5:0]};\r
  76         4'h6    :   Random={3'b0,Random_sequence[6:0]};\r
  77         4'h7    :   Random={2'b0,Random_sequence[7:0]};\r
  78         4'h8    :   Random={1'b0,Random_sequence[8:0]};\r
  79         4'h9    :   Random={     Random_sequence[9:0]};  \r
  80         default :   Random={     Random_sequence[9:0]};\r
  81     endcase\r
  82 \r
  83 always @ (posedge Clk or posedge Reset)\r
  84     if (Reset)\r
  85         Slot_time_counter       <=0;\r
  86     else if(Init)\r
  87         Slot_time_counter       <=0;\r
  88     else if(!Random_time_meet)\r
  89         Slot_time_counter       <=Slot_time_counter+1;\r
  90     \r
  91 always @ (posedge Clk or posedge Reset)\r
  92     if (Reset)\r
  93         Random_counter      <=0;\r
  94     else if (Init)\r
  95         Random_counter      <=Random;\r
  96     else if (Random_counter!=0&&Slot_time_counter==255)\r
  97         Random_counter      <=Random_counter -1 ;\r
  98         \r
  99 always @ (posedge Clk or posedge Reset)\r
 100     if (Reset)\r
 101         Random_time_meet    <=1;\r
 102     else if (Init)\r
 103         Random_time_meet    <=0;\r
 104     else if (Random_counter==0)\r
 105         Random_time_meet    <=1;\r
 106         \r
 107 endmodule\r
 108 \r
 109 \r