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   1 //////////////////////////////////////////////////////////////////////\r
   2 ////                                                              ////\r
   3 ////  MAC_tx_FF.v                                                 ////\r
   4 ////                                                              ////\r
   5 ////  This file is part of the Ethernet IP core project           ////\r
   6 ////  http://www.opencores.org/projects.cgi/web/ethernet_tri_mode/////\r
   7 ////                                                              ////\r
   8 ////  Author(s):                                                  ////\r
   9 ////      - Jon Gao (gaojon@yahoo.com)                            ////\r
  10 ////                                                              ////\r
  11 ////                                                              ////\r
  12 //////////////////////////////////////////////////////////////////////\r
  13 ////                                                              ////\r
  14 //// Copyright (C) 2001 Authors                                   ////\r
  15 ////                                                              ////\r
  16 //// This source file may be used and distributed without         ////\r
  17 //// restriction provided that this copyright statement is not    ////\r
  18 //// removed from the file and that any derivative work contains  ////\r
  19 //// the original copyright notice and the associated disclaimer. ////\r
  20 ////                                                              ////\r
  21 //// This source file is free software; you can redistribute it   ////\r
  22 //// and/or modify it under the terms of the GNU Lesser General   ////\r
  23 //// Public License as published by the Free Software Foundation; ////\r
  24 //// either version 2.1 of the License, or (at your option) any   ////\r
  25 //// later version.                                               ////\r
  26 ////                                                              ////\r
  27 //// This source is distributed in the hope that it will be       ////\r
  28 //// useful, but WITHOUT ANY WARRANTY; without even the implied   ////\r
  29 //// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////\r
  30 //// PURPOSE.  See the GNU Lesser General Public License for more ////\r
  31 //// details.                                                     ////\r
  32 ////                                                              ////\r
  33 //// You should have received a copy of the GNU Lesser General    ////\r
  34 //// Public License along with this source; if not, download it   ////\r
  35 //// from http://www.opencores.org/lgpl.shtml                     ////\r
  36 ////                                                              ////\r
  37 //////////////////////////////////////////////////////////////////////\r
  38 \r
  39 module MAC_tx_FF \r
  40   #(parameter TX_FF_DEPTH = 9)\r
  41     (input           Reset               ,\r
  42      input           Clk_MAC             ,\r
  43      input           Clk_SYS             ,\r
  44      //MAC_tx_ctrl\r
  45      output reg [7:0]Fifo_data           ,\r
  46      input           Fifo_rd             ,\r
  47      input           Fifo_rd_finish      ,\r
  48      input           Fifo_rd_retry       ,\r
  49      output reg      Fifo_eop            ,\r
  50      output reg      Fifo_da             ,\r
  51      output reg      Fifo_ra             ,\r
  52      output reg      Fifo_data_err_empty ,\r
  53      output          Fifo_data_err_full  ,\r
  54      //user interface \r
  55      output reg      Tx_mac_wa           ,\r
  56      input           Tx_mac_wr           ,\r
  57      input   [31:0]  Tx_mac_data         ,\r
  58      input   [1:0]   Tx_mac_BE           ,//big endian\r
  59      input           Tx_mac_sop          ,\r
  60      input           Tx_mac_eop          ,\r
  61      //host interface \r
  62      input           FullDuplex          ,\r
  63      input   [4:0]   Tx_Hwmark           ,\r
  64      input   [4:0]   Tx_Lwmark           ,\r
  65      output  [31:0]  debug0,\r
  66      output [31:0]   debug1\r
  67      );\r
  68 \r
  69 //******************************************************************************\r
  70 //internal signals                                                              \r
  71 //******************************************************************************\r
  72 localparam       MAC_byte3               =4'd00;     \r
  73 localparam       MAC_byte2               =4'd01;\r
  74 localparam       MAC_byte1               =4'd02; \r
  75 localparam       MAC_byte0               =4'd03; \r
  76 localparam       MAC_wait_finish         =4'd04;\r
  77 localparam       MAC_retry               =4'd08;\r
  78 localparam       MAC_idle                =4'd09;\r
  79 localparam       MAC_FFEmpty             =4'd10;\r
  80 localparam       MAC_FFEmpty_drop        =4'd11;\r
  81 localparam       MAC_pkt_sub             =4'd12;\r
  82 localparam       MAC_FF_Err              =4'd13;\r
  83 \r
  84 \r
  85 reg [3:0]       Next_state_MAC              ;\r
  86 \r
  87 \r
  88 localparam       SYS_idle                =4'd0;\r
  89 localparam       SYS_WaitSop             =4'd1;\r
  90 localparam       SYS_SOP                 =4'd2;\r
  91 localparam       SYS_MOP                 =4'd3;\r
  92 localparam       SYS_DROP                =4'd4;\r
  93 localparam       SYS_EOP_ok              =4'd5;  \r
  94 localparam       SYS_FFEmpty             =4'd6;         \r
  95 localparam       SYS_EOP_err             =4'd7;\r
  96 localparam       SYS_SOP_err             =4'd8;\r
  97 \r
  98 reg [3:0]       Next_state_SYS;\r
  99 \r
 100 reg [TX_FF_DEPTH-1:0]       Add_wr          ;\r
 101 reg [TX_FF_DEPTH-1:0]       Add_wr_ungray   ;\r
 102 reg [TX_FF_DEPTH-1:0]       Add_wr_gray     ;\r
 103 reg [TX_FF_DEPTH-1:0]       Add_wr_gray_dl1 ;\r
 104 reg [TX_FF_DEPTH-1:0]       Add_wr_gray_dl2 ;\r
 105 \r
 106 reg [TX_FF_DEPTH-1:0]       Add_rd          ;\r
 107 reg [TX_FF_DEPTH-1:0]       Add_rd_reg      ;\r
 108 reg [TX_FF_DEPTH-1:0]       Add_rd_gray     ;\r
 109 reg [TX_FF_DEPTH-1:0]       Add_rd_gray_dl1 ;\r
 110 reg [TX_FF_DEPTH-1:0]       Add_rd_gray_dl2 ;\r
 111 reg [TX_FF_DEPTH-1:0]       Add_rd_ungray   ;\r
 112 wire[35:0]      Din             ;\r
 113 wire[35:0]      Dout            ;\r
 114 reg             Wr_en           ;\r
 115 wire[TX_FF_DEPTH-1:0]                  Add_wr_pluse;\r
 116 wire[TX_FF_DEPTH-1:0]                  Add_wr_pluse_pluse;\r
 117 reg [TX_FF_DEPTH-1:TX_FF_DEPTH-5] Add_rd_reg_dl1;\r
 118 \r
 119 reg [3:0]       Current_state_MAC;\r
 120 reg [3:0]       Current_state_MAC_reg;\r
 121 reg [3:0]       Current_state_SYS;\r
 122 reg             Full;\r
 123 reg             AlmostFull;\r
 124 reg             Empty;\r
 125 reg [35:0]      Dout_reg;\r
 126 reg             Packet_number_sub_edge;\r
 127 reg             Packet_number_add;\r
 128 reg [5:0]       Packet_number_inFF;\r
 129 reg [5:0]       Packet_number_inFF_reg;\r
 130 reg             Dout_reg_en;\r
 131 reg             Add_rd_add;\r
 132 \r
 133 \r
 134 reg             Tx_mac_wr_dl1           ;\r
 135 reg [31:0]      Tx_mac_data_dl1         ;\r
 136 reg [1:0]       Tx_mac_BE_dl1           ;\r
 137 reg             FF_FullErr              ;\r
 138 wire[1:0]       Dout_BE                 ;\r
 139 wire            Dout_eop                ;\r
 140 wire            Dout_err                ;\r
 141 wire[31:0]      Dout_data               ;     \r
 142 reg             Packet_number_sub_dl1   ;\r
 143 reg             Packet_number_sub_dl2   ;\r
 144 reg [4:0]       Fifo_data_count         ;\r
 145 reg             Fifo_ra_tmp             ;      \r
 146 reg             Pkt_sub_apply_tmp       ;\r
 147 reg             Pkt_sub_apply           ;\r
 148 reg             Add_rd_reg_rdy_tmp      ;\r
 149 reg             Add_rd_reg_rdy          ;   \r
 150 reg             Add_rd_reg_rdy_dl1      ;   \r
 151 reg             Add_rd_reg_rdy_dl2      ;\r
 152 reg [4:0]       Tx_Hwmark_pl            ;\r
 153 reg [4:0]       Tx_Lwmark_pl            ;\r
 154 reg             Add_rd_jump_tmp         ;\r
 155 reg             Add_rd_jump_tmp_pl1     ;\r
 156 reg             Add_rd_jump             ;\r
 157 reg             Add_rd_jump_wr_pl1      ;\r
 158 \r
 159 //******************************************************************************\r
 160 //write data to from FF .\r
 161 //domain Clk_SYS\r
 162 //******************************************************************************\r
 163 always @ (posedge Clk_SYS or posedge Reset)\r
 164     if (Reset)\r
 165         Current_state_SYS   <=SYS_idle;\r
 166     else\r
 167         Current_state_SYS   <=Next_state_SYS;\r
 168         \r
 169 always @ (Current_state_SYS or Tx_mac_wr or Tx_mac_sop or Full or AlmostFull \r
 170             or Tx_mac_eop )\r
 171     case (Current_state_SYS)\r
 172         SYS_idle:\r
 173             if (Tx_mac_wr&&Tx_mac_sop&&!Full)\r
 174                 Next_state_SYS      =SYS_SOP;\r
 175             else\r
 176                 Next_state_SYS      =Current_state_SYS ;\r
 177         SYS_SOP:\r
 178                 Next_state_SYS      =SYS_MOP;\r
 179         SYS_MOP:\r
 180             if (AlmostFull)\r
 181                 Next_state_SYS      =SYS_DROP;\r
 182             else if (Tx_mac_wr&&Tx_mac_sop)\r
 183                 Next_state_SYS      =SYS_SOP_err;\r
 184             else if (Tx_mac_wr&&Tx_mac_eop)\r
 185                 Next_state_SYS      =SYS_EOP_ok;\r
 186             else\r
 187                 Next_state_SYS      =Current_state_SYS ;\r
 188         SYS_EOP_ok:\r
 189             if (Tx_mac_wr&&Tx_mac_sop)\r
 190                 Next_state_SYS      =SYS_SOP;\r
 191             else\r
 192                 Next_state_SYS      =SYS_idle;\r
 193         SYS_EOP_err:\r
 194             if (Tx_mac_wr&&Tx_mac_sop)\r
 195                 Next_state_SYS      =SYS_SOP;\r
 196             else\r
 197                 Next_state_SYS      =SYS_idle;\r
 198         SYS_SOP_err:\r
 199                 Next_state_SYS      =SYS_DROP;\r
 200         SYS_DROP: //FIFO overflow           \r
 201             if (Tx_mac_wr&&Tx_mac_eop)\r
 202                 Next_state_SYS      =SYS_EOP_err;\r
 203             else \r
 204                 Next_state_SYS      =Current_state_SYS ;\r
 205         default:\r
 206                 Next_state_SYS      =SYS_idle;\r
 207     endcase\r
 208     \r
 209 //delay signals \r
 210 always @ (posedge Clk_SYS or posedge Reset)\r
 211     if (Reset)\r
 212         begin       \r
 213         Tx_mac_wr_dl1           <=0;\r
 214         Tx_mac_data_dl1         <=0;\r
 215         Tx_mac_BE_dl1           <=0;\r
 216         end  \r
 217     else\r
 218         begin       \r
 219         Tx_mac_wr_dl1           <=Tx_mac_wr     ;\r
 220         Tx_mac_data_dl1         <=Tx_mac_data   ;\r
 221         Tx_mac_BE_dl1           <=Tx_mac_BE     ;\r
 222         end \r
 223 \r
 224 always @(Current_state_SYS) \r
 225     if (Current_state_SYS==SYS_EOP_err)\r
 226         FF_FullErr      =1;\r
 227     else\r
 228         FF_FullErr      =0; \r
 229 \r
 230 reg     Tx_mac_eop_gen;\r
 231 \r
 232 always @(Current_state_SYS) \r
 233     if (Current_state_SYS==SYS_EOP_err||Current_state_SYS==SYS_EOP_ok)\r
 234         Tx_mac_eop_gen      =1;\r
 235     else\r
 236         Tx_mac_eop_gen      =0; \r
 237                 \r
 238 assign  Din={Tx_mac_eop_gen,FF_FullErr,Tx_mac_BE_dl1,Tx_mac_data_dl1};\r
 239 \r
 240 always @(Current_state_SYS or Tx_mac_wr_dl1)\r
 241     if ((Current_state_SYS==SYS_SOP||Current_state_SYS==SYS_EOP_ok||\r
 242         Current_state_SYS==SYS_MOP||Current_state_SYS==SYS_EOP_err)&&Tx_mac_wr_dl1)\r
 243         Wr_en   = 1;\r
 244     else\r
 245         Wr_en   = 0;\r
 246         \r
 247         \r
 248 //\r
 249         \r
 250         \r
 251 always @ (posedge Reset or posedge Clk_SYS)\r
 252     if (Reset)\r
 253         Add_wr_gray         <=0;\r
 254     else \r
 255       begin : Add_wr_gray_loop\r
 256         integer i;\r
 257         Add_wr_gray[TX_FF_DEPTH-1]      <=Add_wr[TX_FF_DEPTH-1];\r
 258         for (i=TX_FF_DEPTH-2;i>=0;i=i-1)\r
 259           Add_wr_gray[i] <=Add_wr[i+1]^Add_wr[i];\r
 260       end\r
 261 \r
 262 always @ (posedge Clk_SYS or posedge Reset)\r
 263     if (Reset)\r
 264         Add_rd_gray_dl1         <=0;\r
 265     else\r
 266         Add_rd_gray_dl1         <=Add_rd_gray;\r
 267 \r
 268    always @(posedge Clk_SYS or posedge Reset)\r
 269      if (Reset)\r
 270        Add_rd_gray_dl2 <= 0;\r
 271      else\r
 272        Add_rd_gray_dl2 <= Add_rd_gray_dl1;\r
 273    \r
 274 always @ (posedge Clk_SYS or posedge Reset)\r
 275     if (Reset)\r
 276         Add_rd_jump_wr_pl1  <=0;\r
 277     else        \r
 278         Add_rd_jump_wr_pl1  <=Add_rd_jump;\r
 279                     \r
 280 always @ (posedge Clk_SYS or posedge Reset)\r
 281     if (Reset)\r
 282         Add_rd_ungray       =0;\r
 283     else if (!Add_rd_jump_wr_pl1)       \r
 284       begin : Add_rd_ungray_loop\r
 285         integer i;\r
 286         Add_rd_ungray[TX_FF_DEPTH-1] = Add_rd_gray_dl2[TX_FF_DEPTH-1];\r
 287         for (i=TX_FF_DEPTH-2;i>=0;i=i-1)\r
 288           Add_rd_ungray[i] = Add_rd_ungray[i+1]^Add_rd_gray_dl2[i];\r
 289       end\r
 290 \r
 291 assign          Add_wr_pluse        =Add_wr+1;\r
 292 assign          Add_wr_pluse_pluse  =Add_wr+4;\r
 293 \r
 294 always @ (Add_wr_pluse or Add_rd_ungray)\r
 295     if (Add_wr_pluse==Add_rd_ungray)\r
 296         Full    =1;\r
 297     else\r
 298         Full    =0;\r
 299 \r
 300 always @ (posedge Clk_SYS or posedge Reset)\r
 301     if (Reset)\r
 302         AlmostFull  <=0;\r
 303     else if (Add_wr_pluse_pluse==Add_rd_ungray)\r
 304         AlmostFull  <=1;\r
 305     else\r
 306         AlmostFull  <=0;\r
 307         \r
 308 always @ (posedge Clk_SYS or posedge Reset)\r
 309     if (Reset)\r
 310         Add_wr  <= 0;\r
 311     else if (Wr_en&&!Full)\r
 312         Add_wr  <= Add_wr +1;\r
 313         \r
 314 always @ (posedge Clk_SYS or posedge Reset)\r
 315     if (Reset)\r
 316         begin\r
 317         Packet_number_sub_dl1   <=0;\r
 318         Packet_number_sub_dl2   <=0;\r
 319         end\r
 320     else \r
 321         begin\r
 322         Packet_number_sub_dl1   <=Pkt_sub_apply;\r
 323         Packet_number_sub_dl2   <=Packet_number_sub_dl1;\r
 324         end\r
 325         \r
 326 always @ (posedge Clk_SYS or posedge Reset)\r
 327     if (Reset)\r
 328         Packet_number_sub_edge  <=0;\r
 329     else if (Packet_number_sub_dl1&!Packet_number_sub_dl2)\r
 330         Packet_number_sub_edge  <=1;\r
 331     else\r
 332         Packet_number_sub_edge  <=0;\r
 333 \r
 334 always @ (posedge Clk_SYS or posedge Reset)\r
 335     if (Reset)\r
 336         Packet_number_add       <=0;    \r
 337     else if (Current_state_SYS==SYS_EOP_ok||Current_state_SYS==SYS_EOP_err)\r
 338         Packet_number_add       <=1;\r
 339     else\r
 340         Packet_number_add       <=0;    \r
 341         \r
 342 \r
 343 always @ (posedge Clk_SYS or posedge Reset)\r
 344     if (Reset)\r
 345         Packet_number_inFF      <=0;\r
 346     else if (Packet_number_add&&!Packet_number_sub_edge)\r
 347         Packet_number_inFF      <=Packet_number_inFF + 1'b1;\r
 348     else if (!Packet_number_add&&Packet_number_sub_edge)\r
 349         Packet_number_inFF      <=Packet_number_inFF - 1'b1;\r
 350 \r
 351 \r
 352 always @ (posedge Clk_SYS or posedge Reset)\r
 353     if (Reset)\r
 354         Packet_number_inFF_reg      <=0;\r
 355     else\r
 356         Packet_number_inFF_reg      <=Packet_number_inFF;\r
 357 \r
 358 always @ (posedge Clk_SYS or posedge Reset)\r
 359     if (Reset)\r
 360         begin\r
 361         Add_rd_reg_rdy_dl1          <=0;\r
 362         Add_rd_reg_rdy_dl2          <=0;\r
 363         end\r
 364     else\r
 365         begin\r
 366         Add_rd_reg_rdy_dl1          <=Add_rd_reg_rdy;\r
 367         Add_rd_reg_rdy_dl2          <=Add_rd_reg_rdy_dl1;\r
 368         end     \r
 369 \r
 370 always @ (posedge Clk_SYS or posedge Reset)\r
 371     if (Reset)\r
 372         Add_rd_reg_dl1              <=0;\r
 373     else if (Add_rd_reg_rdy_dl1&!Add_rd_reg_rdy_dl2)\r
 374         Add_rd_reg_dl1              <=Add_rd_reg[TX_FF_DEPTH-1:TX_FF_DEPTH-5];\r
 375 \r
 376 \r
 377 \r
 378 always @ (posedge Clk_SYS or posedge Reset)\r
 379     if (Reset)\r
 380         Fifo_data_count     <=0;\r
 381     else if (FullDuplex)\r
 382         Fifo_data_count     <=Add_wr[TX_FF_DEPTH-1:TX_FF_DEPTH-5]-Add_rd_ungray[TX_FF_DEPTH-1:TX_FF_DEPTH-5];\r
 383     else\r
 384         Fifo_data_count     <=Add_wr[TX_FF_DEPTH-1:TX_FF_DEPTH-5]-Add_rd_reg_dl1[TX_FF_DEPTH-1:TX_FF_DEPTH-5]; //for half duplex backoff requirement\r
 385         \r
 386 \r
 387 always @ (posedge Clk_SYS or posedge Reset)\r
 388     if (Reset)\r
 389         Fifo_ra_tmp <=0;    \r
 390     else if (Packet_number_inFF_reg>=1||Fifo_data_count>=Tx_Lwmark)\r
 391         Fifo_ra_tmp <=1;        \r
 392     else \r
 393         Fifo_ra_tmp <=0;\r
 394 \r
 395 always @ (posedge Clk_SYS or posedge Reset)\r
 396     if (Reset)\r
 397         begin \r
 398         Tx_Hwmark_pl        <=0;\r
 399         Tx_Lwmark_pl        <=0;    \r
 400         end\r
 401     else\r
 402         begin \r
 403         Tx_Hwmark_pl        <=Tx_Hwmark;\r
 404         Tx_Lwmark_pl        <=Tx_Lwmark;    \r
 405         end    \r
 406     \r
 407 always @ (posedge Clk_SYS or posedge Reset)\r
 408     if (Reset)\r
 409         Tx_mac_wa   <=0;  \r
 410     else if (Fifo_data_count>=Tx_Hwmark_pl)\r
 411         Tx_mac_wa   <=0;\r
 412     else if (Fifo_data_count<Tx_Lwmark_pl)\r
 413         Tx_mac_wa   <=1;\r
 414 \r
 415 //******************************************************************************\r
 416 //rd data to from FF .\r
 417 //domain Clk_MAC\r
 418 //******************************************************************************\r
 419 reg[35:0]   Dout_dl1;\r
 420 \r
 421 always @ (posedge Clk_MAC or posedge Reset)\r
 422     if (Reset)\r
 423         Dout_dl1    <=0;\r
 424     else\r
 425         Dout_dl1    <=Dout;\r
 426 \r
 427 always @ (Current_state_MAC or Next_state_MAC)\r
 428     if ((Current_state_MAC==MAC_idle||Current_state_MAC==MAC_byte0)&&Next_state_MAC==MAC_byte3)\r
 429         Dout_reg_en     =1;\r
 430     else\r
 431         Dout_reg_en     =0; \r
 432             \r
 433 always @ (posedge Clk_MAC or posedge Reset)\r
 434     if (Reset)\r
 435         Dout_reg        <=0;\r
 436     else if (Dout_reg_en)\r
 437         Dout_reg    <=Dout_dl1;     \r
 438         \r
 439 assign {Dout_eop,Dout_err,Dout_BE,Dout_data}=Dout_reg;\r
 440 \r
 441 always @ (posedge Clk_MAC or posedge Reset)\r
 442     if (Reset)\r
 443         Current_state_MAC   <=MAC_idle;\r
 444     else\r
 445         Current_state_MAC   <=Next_state_MAC;       \r
 446         \r
 447 always @ (Current_state_MAC or Fifo_rd or Dout_BE or Dout_eop or Fifo_rd_retry\r
 448             or Fifo_rd_finish or Empty or Fifo_rd or Fifo_eop)\r
 449         case (Current_state_MAC)\r
 450             MAC_idle:\r
 451                 if (Empty&&Fifo_rd)\r
 452                     Next_state_MAC=MAC_FF_Err;\r
 453                 else if (Fifo_rd)\r
 454                     Next_state_MAC=MAC_byte3;\r
 455                 else\r
 456                     Next_state_MAC=Current_state_MAC;\r
 457             MAC_byte3:\r
 458                 if (Fifo_rd_retry)\r
 459                     Next_state_MAC=MAC_retry;           \r
 460                 else if (Fifo_eop)\r
 461                     Next_state_MAC=MAC_wait_finish;\r
 462                 else if (Fifo_rd&&!Fifo_eop)\r
 463                     Next_state_MAC=MAC_byte2;\r
 464                 else\r
 465                     Next_state_MAC=Current_state_MAC;\r
 466             MAC_byte2:\r
 467                 if (Fifo_rd_retry)\r
 468                     Next_state_MAC=MAC_retry;\r
 469                 else if (Fifo_eop)\r
 470                     Next_state_MAC=MAC_wait_finish;\r
 471                 else if (Fifo_rd&&!Fifo_eop)\r
 472                     Next_state_MAC=MAC_byte1;\r
 473                 else\r
 474                     Next_state_MAC=Current_state_MAC;       \r
 475             MAC_byte1:\r
 476                 if (Fifo_rd_retry)\r
 477                     Next_state_MAC=MAC_retry;\r
 478                 else if (Fifo_eop)\r
 479                     Next_state_MAC=MAC_wait_finish;\r
 480                 else if (Fifo_rd&&!Fifo_eop)\r
 481                     Next_state_MAC=MAC_byte0;\r
 482                 else\r
 483                     Next_state_MAC=Current_state_MAC;   \r
 484             MAC_byte0:\r
 485                 if (Empty&&Fifo_rd&&!Fifo_eop)\r
 486                     Next_state_MAC=MAC_FFEmpty;\r
 487                 else if (Fifo_rd_retry)\r
 488                     Next_state_MAC=MAC_retry;\r
 489                 else if (Fifo_eop)\r
 490                     Next_state_MAC=MAC_wait_finish;     \r
 491                 else if (Fifo_rd&&!Fifo_eop)\r
 492                     Next_state_MAC=MAC_byte3;\r
 493                 else\r
 494                     Next_state_MAC=Current_state_MAC;   \r
 495             MAC_retry:\r
 496                     Next_state_MAC=MAC_idle;\r
 497             MAC_wait_finish:\r
 498                 if (Fifo_rd_finish)\r
 499                     Next_state_MAC=MAC_pkt_sub;\r
 500                 else\r
 501                     Next_state_MAC=Current_state_MAC;\r
 502             MAC_pkt_sub:\r
 503                     Next_state_MAC=MAC_idle;\r
 504             MAC_FFEmpty:\r
 505                 if (!Empty)\r
 506                     Next_state_MAC=MAC_byte3;\r
 507                 else\r
 508                     Next_state_MAC=Current_state_MAC;\r
 509             MAC_FF_Err:  //stopped state-machine need change                         \r
 510                     Next_state_MAC=Current_state_MAC;\r
 511             default\r
 512                     Next_state_MAC=MAC_idle;    \r
 513         endcase\r
 514 //\r
 515 always @ (posedge Reset or posedge Clk_MAC)\r
 516     if (Reset)\r
 517         Add_rd_gray         <=0;\r
 518     else \r
 519       begin : Add_rd_gray_loop\r
 520         integer i;\r
 521         Add_rd_gray[TX_FF_DEPTH-1]      <=Add_rd[TX_FF_DEPTH-1];\r
 522         for (i=TX_FF_DEPTH-2;i>=0;i=i-1)\r
 523           Add_rd_gray[i] <= Add_rd[i+1]^Add_rd[i];\r
 524       end\r
 525 //\r
 526 \r
 527 always @ (posedge Clk_MAC or posedge Reset)\r
 528     if (Reset)\r
 529         Add_wr_gray_dl1     <=0;\r
 530     else\r
 531         Add_wr_gray_dl1     <=Add_wr_gray;\r
 532 \r
 533 always @ (posedge Clk_MAC or posedge Reset)\r
 534     if (Reset)\r
 535         Add_wr_gray_dl2     <=0;\r
 536     else\r
 537         Add_wr_gray_dl2     <=Add_wr_gray_dl1;\r
 538             \r
 539 always @ (posedge Clk_MAC or posedge Reset)\r
 540     if (Reset)\r
 541         Add_wr_ungray       =0;\r
 542     else        \r
 543       begin : Add_wr_ungray_loop\r
 544         integer i;\r
 545         Add_wr_ungray[TX_FF_DEPTH-1] = Add_wr_gray_dl2[TX_FF_DEPTH-1];\r
 546         for (i=TX_FF_DEPTH-2;i>=0;i=i-1)\r
 547           Add_wr_ungray[i] = Add_wr_ungray[i+1]^Add_wr_gray_dl2[i];     \r
 548       end           \r
 549 \r
 550 //empty     \r
 551 always @ (posedge Clk_MAC or posedge Reset)\r
 552     if (Reset)      \r
 553         Empty   <=1;\r
 554     else if (Add_rd==Add_wr_ungray)\r
 555         Empty   <=1;\r
 556     else\r
 557         Empty   <=0;    \r
 558         \r
 559 //ra\r
 560 always @ (posedge Clk_MAC or posedge Reset)\r
 561     if (Reset)\r
 562         Fifo_ra <=0;\r
 563     else\r
 564         Fifo_ra <=Fifo_ra_tmp;\r
 565 \r
 566 \r
 567 \r
 568 always @ (posedge Clk_MAC or posedge Reset)     \r
 569     if (Reset)  \r
 570         Pkt_sub_apply_tmp   <=0;\r
 571     else if (Current_state_MAC==MAC_pkt_sub)\r
 572         Pkt_sub_apply_tmp   <=1;\r
 573     else\r
 574         Pkt_sub_apply_tmp   <=0;\r
 575         \r
 576 always @ (posedge Clk_MAC or posedge Reset) \r
 577     if (Reset)\r
 578         Pkt_sub_apply   <=0;\r
 579     else if ((Current_state_MAC==MAC_pkt_sub)||Pkt_sub_apply_tmp)\r
 580         Pkt_sub_apply   <=1;\r
 581     else                \r
 582         Pkt_sub_apply   <=0;\r
 583 \r
 584 //reg Add_rd for collison retry\r
 585 always @ (posedge Clk_MAC or posedge Reset)\r
 586     if (Reset)\r
 587         Add_rd_reg      <=0;\r
 588     else if (Fifo_rd_finish)\r
 589         Add_rd_reg      <=Add_rd;\r
 590 \r
 591 always @ (posedge Clk_MAC or posedge Reset)\r
 592     if (Reset)\r
 593         Add_rd_reg_rdy_tmp      <=0;\r
 594     else if (Fifo_rd_finish)\r
 595         Add_rd_reg_rdy_tmp      <=1;\r
 596     else\r
 597         Add_rd_reg_rdy_tmp      <=0;\r
 598         \r
 599 always @ (posedge Clk_MAC or posedge Reset)\r
 600     if (Reset)\r
 601         Add_rd_reg_rdy      <=0;\r
 602     else if (Fifo_rd_finish||Add_rd_reg_rdy_tmp)\r
 603         Add_rd_reg_rdy      <=1;\r
 604     else\r
 605         Add_rd_reg_rdy      <=0;         \r
 606  \r
 607 \r
 608 always @ (Current_state_MAC or Next_state_MAC)\r
 609     if ((Current_state_MAC==MAC_idle||Current_state_MAC==MAC_byte0)&&Next_state_MAC==MAC_byte3)\r
 610         Add_rd_add  =1;\r
 611     else\r
 612         Add_rd_add  =0;\r
 613         \r
 614         \r
 615 always @ (posedge Clk_MAC or posedge Reset)\r
 616     if (Reset)\r
 617         Add_rd          <=0;\r
 618     else if (Current_state_MAC==MAC_retry)\r
 619         Add_rd          <= Add_rd_reg;\r
 620     else if (Add_rd_add)\r
 621         Add_rd          <= Add_rd + 1;  \r
 622                     \r
 623 always @ (posedge Clk_MAC or posedge Reset)\r
 624         if (Reset)\r
 625             Add_rd_jump_tmp <=0;\r
 626         else if (Current_state_MAC==MAC_retry)\r
 627             Add_rd_jump_tmp <=1;\r
 628         else\r
 629             Add_rd_jump_tmp <=0;\r
 630 \r
 631 always @ (posedge Clk_MAC or posedge Reset)\r
 632         if (Reset)\r
 633             Add_rd_jump_tmp_pl1 <=0;\r
 634         else\r
 635             Add_rd_jump_tmp_pl1 <=Add_rd_jump_tmp;       \r
 636             \r
 637 always @ (posedge Clk_MAC or posedge Reset)\r
 638         if (Reset)\r
 639             Add_rd_jump <=0;\r
 640         else if (Current_state_MAC==MAC_retry)\r
 641             Add_rd_jump <=1;\r
 642         else if (Add_rd_jump_tmp_pl1)\r
 643             Add_rd_jump <=0;    \r
 644                                                 \r
 645 //gen Fifo_data \r
 646 \r
 647         \r
 648 always @ (Dout_data or Current_state_MAC)\r
 649     case (Current_state_MAC)\r
 650         MAC_byte3:\r
 651             Fifo_data   =Dout_data[31:24];\r
 652         MAC_byte2:\r
 653             Fifo_data   =Dout_data[23:16];\r
 654         MAC_byte1:\r
 655             Fifo_data   =Dout_data[15:8];\r
 656         MAC_byte0:\r
 657             Fifo_data   =Dout_data[7:0];\r
 658         default:\r
 659             Fifo_data   =0;     \r
 660     endcase\r
 661         \r
 662 always @ (posedge Clk_MAC or posedge Reset)\r
 663     if (Reset)\r
 664         Fifo_da         <=0;\r
 665     else if ((Current_state_MAC==MAC_byte0||Current_state_MAC==MAC_byte1||\r
 666               Current_state_MAC==MAC_byte2||Current_state_MAC==MAC_byte3)&&Fifo_rd&&!Fifo_eop)\r
 667         Fifo_da         <=1;\r
 668     else\r
 669         Fifo_da         <=0;\r
 670 \r
 671 //gen Fifo_data_err_empty\r
 672 assign  Fifo_data_err_full=Dout_err;\r
 673 //gen Fifo_data_err_empty\r
 674 always @ (posedge Clk_MAC or posedge Reset)\r
 675     if (Reset)\r
 676         Current_state_MAC_reg   <=0;\r
 677     else\r
 678         Current_state_MAC_reg   <=Current_state_MAC;\r
 679         \r
 680 always @ (posedge Clk_MAC or posedge Reset)\r
 681     if (Reset)\r
 682         Fifo_data_err_empty     <=0;\r
 683     else if (Current_state_MAC_reg==MAC_FFEmpty)\r
 684         Fifo_data_err_empty     <=1;\r
 685     else\r
 686         Fifo_data_err_empty     <=0;\r
 687     \r
 688 //always @ (posedge Clk_MAC)\r
 689 //    if (Current_state_MAC_reg==MAC_FF_Err)  \r
 690 //        begin\r
 691 //        $finish(2); \r
 692 //        $display("mac_tx_FF meet error status at time :%t",$time);\r
 693 //        end\r
 694 \r
 695 //gen Fifo_eop aligned to last valid data byte\r
 696 always @ ( Current_state_MAC or Dout_eop or Dout_BE )\r
 697   if ( ( ( Current_state_MAC==MAC_byte0 && Dout_BE==2'b00 ) ||\r
 698          ( Current_state_MAC==MAC_byte1 && Dout_BE==2'b11 ) ||\r
 699          ( Current_state_MAC==MAC_byte2 && Dout_BE==2'b10 ) ||\r
 700          ( Current_state_MAC==MAC_byte3 && Dout_BE==2'b01 ) ) && Dout_eop )\r
 701     Fifo_eop = 1;\r
 702   else\r
 703     Fifo_eop = 0;\r
 704    \r
 705    // Dual port RAM for FIFO\r
 706    ram_2port #(.DWIDTH(36),.AWIDTH(TX_FF_DEPTH)) mac_tx_ff_ram\r
 707      (.clka(Clk_SYS),.ena(1'b1),.wea(Wr_en),.addra(Add_wr),.dia(Din),.doa(),\r
 708       .clkb(Clk_MAC),.enb(1'b1),.web(1'b0),.addrb(Add_rd),.dib(36'b0),.dob(Dout) );\r
 709 \r
 710    assign debug0 = \r
 711           { { 5'd0, Empty, Full, AlmostFull },\r
 712             { Current_state_SYS, Current_state_MAC },\r
 713             { Fifo_rd, Fifo_rd_finish, Fifo_rd_retry, Fifo_eop, Fifo_da, Fifo_ra, Fifo_data_err_empty, Fifo_data_err_full },\r
 714             { 2'b0, Dout_BE, Tx_mac_wa, Tx_mac_wr, Tx_mac_sop, Tx_mac_eop} };\r
 715             \r
 716    assign debug1 = \r
 717           { { 8'd0 },\r
 718             { 8'd0 },\r
 719             { 8'd0 },\r
 720             { 8'd0 } };\r
 721    \r
 722 endmodule // MAC_tx_FF\r