1 //////////////////////////////////////////////////////////////////////
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5 //// This file is part of the Ethernet IP core project ////
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6 //// http://www.opencores.org/projects.cgi/web/ethernet_tri_mode/////
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9 //// - Jon Gao (gaojon@yahoo.com) ////
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12 //////////////////////////////////////////////////////////////////////
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14 //// Copyright (C) 2001 Authors ////
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16 //// This source file may be used and distributed without ////
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17 //// restriction provided that this copyright statement is not ////
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18 //// removed from the file and that any derivative work contains ////
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19 //// the original copyright notice and the associated disclaimer. ////
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21 //// This source file is free software; you can redistribute it ////
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22 //// and/or modify it under the terms of the GNU Lesser General ////
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23 //// Public License as published by the Free Software Foundation; ////
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24 //// either version 2.1 of the License, or (at your option) any ////
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25 //// later version. ////
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27 //// This source is distributed in the hope that it will be ////
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28 //// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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29 //// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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30 //// PURPOSE. See the GNU Lesser General Public License for more ////
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33 //// You should have received a copy of the GNU Lesser General ////
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34 //// Public License along with this source; if not, download it ////
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35 //// from http://www.opencores.org/lgpl.shtml ////
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37 //////////////////////////////////////////////////////////////////////
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39 // CVS Revision History
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41 // $Log: CRC_chk.v,v $
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42 // Revision 1.3 2006/01/19 14:07:54 maverickist
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43 // verification is complete.
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45 // Revision 1.2 2005/12/16 06:44:16 Administrator
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46 // replaced tab with space.
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47 // passed 9.6k length frame test.
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49 // Revision 1.1.1.1 2005/12/13 01:51:45 Administrator
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65 input[7:0] CRC_data ;
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71 //******************************************************************************
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73 //******************************************************************************
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75 //******************************************************************************
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76 //input data width is 8bit, and the first bit is bit[0]
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77 function[31:0] NextCRC;
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82 NewCRC[0]=C[24]^C[30]^D[1]^D[7];
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83 NewCRC[1]=C[25]^C[31]^D[0]^D[6]^C[24]^C[30]^D[1]^D[7];
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84 NewCRC[2]=C[26]^D[5]^C[25]^C[31]^D[0]^D[6]^C[24]^C[30]^D[1]^D[7];
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85 NewCRC[3]=C[27]^D[4]^C[26]^D[5]^C[25]^C[31]^D[0]^D[6];
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86 NewCRC[4]=C[28]^D[3]^C[27]^D[4]^C[26]^D[5]^C[24]^C[30]^D[1]^D[7];
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87 NewCRC[5]=C[29]^D[2]^C[28]^D[3]^C[27]^D[4]^C[25]^C[31]^D[0]^D[6]^C[24]^C[30]^D[1]^D[7];
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88 NewCRC[6]=C[30]^D[1]^C[29]^D[2]^C[28]^D[3]^C[26]^D[5]^C[25]^C[31]^D[0]^D[6];
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89 NewCRC[7]=C[31]^D[0]^C[29]^D[2]^C[27]^D[4]^C[26]^D[5]^C[24]^D[7];
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90 NewCRC[8]=C[0]^C[28]^D[3]^C[27]^D[4]^C[25]^D[6]^C[24]^D[7];
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91 NewCRC[9]=C[1]^C[29]^D[2]^C[28]^D[3]^C[26]^D[5]^C[25]^D[6];
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92 NewCRC[10]=C[2]^C[29]^D[2]^C[27]^D[4]^C[26]^D[5]^C[24]^D[7];
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93 NewCRC[11]=C[3]^C[28]^D[3]^C[27]^D[4]^C[25]^D[6]^C[24]^D[7];
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94 NewCRC[12]=C[4]^C[29]^D[2]^C[28]^D[3]^C[26]^D[5]^C[25]^D[6]^C[24]^C[30]^D[1]^D[7];
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95 NewCRC[13]=C[5]^C[30]^D[1]^C[29]^D[2]^C[27]^D[4]^C[26]^D[5]^C[25]^C[31]^D[0]^D[6];
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96 NewCRC[14]=C[6]^C[31]^D[0]^C[30]^D[1]^C[28]^D[3]^C[27]^D[4]^C[26]^D[5];
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97 NewCRC[15]=C[7]^C[31]^D[0]^C[29]^D[2]^C[28]^D[3]^C[27]^D[4];
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98 NewCRC[16]=C[8]^C[29]^D[2]^C[28]^D[3]^C[24]^D[7];
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99 NewCRC[17]=C[9]^C[30]^D[1]^C[29]^D[2]^C[25]^D[6];
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100 NewCRC[18]=C[10]^C[31]^D[0]^C[30]^D[1]^C[26]^D[5];
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101 NewCRC[19]=C[11]^C[31]^D[0]^C[27]^D[4];
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102 NewCRC[20]=C[12]^C[28]^D[3];
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103 NewCRC[21]=C[13]^C[29]^D[2];
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104 NewCRC[22]=C[14]^C[24]^D[7];
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105 NewCRC[23]=C[15]^C[25]^D[6]^C[24]^C[30]^D[1]^D[7];
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106 NewCRC[24]=C[16]^C[26]^D[5]^C[25]^C[31]^D[0]^D[6];
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107 NewCRC[25]=C[17]^C[27]^D[4]^C[26]^D[5];
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108 NewCRC[26]=C[18]^C[28]^D[3]^C[27]^D[4]^C[24]^C[30]^D[1]^D[7];
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109 NewCRC[27]=C[19]^C[29]^D[2]^C[28]^D[3]^C[25]^C[31]^D[0]^D[6];
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110 NewCRC[28]=C[20]^C[30]^D[1]^C[29]^D[2]^C[26]^D[5];
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111 NewCRC[29]=C[21]^C[31]^D[0]^C[30]^D[1]^C[27]^D[4];
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112 NewCRC[30]=C[22]^C[31]^D[0]^C[28]^D[3];
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113 NewCRC[31]=C[23]^C[29]^D[2];
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118 always @ (posedge Clk or posedge Reset)
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120 CRC_reg <=32'hffffffff;
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122 CRC_reg <=32'hffffffff;
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124 CRC_reg <=NextCRC(CRC_data,CRC_reg);
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126 assign CRC_err = CRC_chk_en&(CRC_reg[31:0] != 32'hc704dd7b);
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