14 reg [WIDTH-1:0] mini_ram[0:15];
15 wire write_to_ram = (set_stb & (set_addr[7:4]==REGNUM[7:4]));
16 wire [3:0] ram_addr = write_to_ram ? set_addr[3:0] : addr;
20 mini_ram[ram_addr] <= set_data;
22 assign q = mini_ram[ram_addr];
24 endmodule // header_ram