1 --------------------------------------------------------------------------------
2 -- This file is owned and controlled by Xilinx and must be used --
3 -- solely for design, simulation, implementation and creation of --
4 -- design files limited to Xilinx devices or technologies. Use --
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6 -- and immediately terminates your license. --
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11 -- AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION --
12 -- OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS --
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26 -- (c) Copyright 1995-2007 Xilinx, Inc. --
27 -- All rights reserved. --
28 --------------------------------------------------------------------------------
29 -- The following code must appear in the VHDL architecture header:
31 ------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG
32 component fifo_xlnx_512x36_2clk
34 din: IN std_logic_VECTOR(35 downto 0);
40 dout: OUT std_logic_VECTOR(35 downto 0);
43 rd_data_count: OUT std_logic_VECTOR(8 downto 0);
44 wr_data_count: OUT std_logic_VECTOR(8 downto 0));
47 -- Synplicity black box declaration
48 attribute syn_black_box : boolean;
49 attribute syn_black_box of fifo_xlnx_512x36_2clk: component is true;
51 -- COMP_TAG_END ------ End COMPONENT Declaration ------------
53 -- The following code must appear in the VHDL architecture
54 -- body. Substitute your own instance name and net names.
56 ------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG
57 your_instance_name : fifo_xlnx_512x36_2clk
68 rd_data_count => rd_data_count,
69 wr_data_count => wr_data_count);
70 -- INST_TAG_END ------ End INSTANTIATION Template ------------
72 -- You must compile the wrapper file fifo_xlnx_512x36_2clk.vhd when simulating
73 -- the core, fifo_xlnx_512x36_2clk. When compiling the wrapper file, be sure to
74 -- reference the XilinxCoreLib VHDL simulation library. For detailed
75 -- instructions, please refer to the "CORE Generator Help".