1 The following files were generated for 'fifo_xlnx_2Kx36_2clk' in directory
2 /home/matt/usrp2/fpga/coregen:
4 fifo_xlnx_2Kx36_2clk.asy:
5 Graphical symbol information file. Used by the ISE tools and some
6 third party tools to create a symbol representing the core.
8 fifo_xlnx_2Kx36_2clk.ngc:
9 Binary Xilinx implementation netlist file containing the information
10 required to implement the module in a Xilinx (R) FPGA.
12 fifo_xlnx_2Kx36_2clk.sym:
13 Please see the core data sheet.
15 fifo_xlnx_2Kx36_2clk.v:
16 Verilog wrapper file provided to support functional simulation.
17 This file contains simulation model customization data that is
18 passed to a parameterized simulation model for the core.
20 fifo_xlnx_2Kx36_2clk.veo:
21 VEO template file containing code that can be used as a model for
22 instantiating a CORE Generator module in a Verilog design.
24 fifo_xlnx_2Kx36_2clk.vhd:
25 VHDL wrapper file provided to support functional simulation. This
26 file contains simulation model customization data that is passed to
27 a parameterized simulation model for the core.
29 fifo_xlnx_2Kx36_2clk.vho:
30 VHO template file containing code that can be used as a model for
31 instantiating a CORE Generator module in a VHDL design.
33 fifo_xlnx_2Kx36_2clk.xco:
34 CORE Generator input file containing the parameters used to
37 fifo_xlnx_2Kx36_2clk_fifo_generator_v4_3_xst_1.ngc_xst.xrpt:
38 Please see the core data sheet.
40 fifo_xlnx_2Kx36_2clk_flist.txt:
41 Text file listing all of the output files produced when a customized
42 core was generated in the CORE Generator.
44 fifo_xlnx_2Kx36_2clk_readme.txt:
45 Text file indicating the files generated and how they are used.
47 fifo_xlnx_2Kx36_2clk_xmdf.tcl:
48 ISE Project Navigator interface file. ISE uses this file to determine
49 how the files output by CORE Generator for the core can be integrated
50 into your ISE project.
53 Please see the Xilinx CORE Generator online help for further details on
54 generated files and how to use them.