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29 // The synthesis directives "translate_off/translate_on" specified below are
30 // supported by Xilinx, Mentor Graphics and Synplicity synthesis
31 // tools. Ensure they are correct for your synthesis tool(s).
33 // You must compile the wrapper file fifo_xlnx_2Kx36_2clk.v when simulating
34 // the core, fifo_xlnx_2Kx36_2clk. When compiling the wrapper file, be sure to
35 // reference the XilinxCoreLib Verilog simulation library. For detailed
36 // instructions, please refer to the "CORE Generator Help".
40 module fifo_xlnx_2Kx36_2clk(
63 output [11 : 0] rd_data_count;
64 output [11 : 0] wr_data_count;
66 // synthesis translate_off
68 FIFO_GENERATOR_V4_3 #(
71 .C_DATA_COUNT_WIDTH(12),
72 .C_DEFAULT_VALUE("BlankString"),
77 .C_FAMILY("spartan3"),
78 .C_FULL_FLAGS_RST_VAL(1),
79 .C_HAS_ALMOST_EMPTY(0),
80 .C_HAS_ALMOST_FULL(0),
84 .C_HAS_MEMINIT_FILE(0),
86 .C_HAS_RD_DATA_COUNT(1),
93 .C_HAS_WR_DATA_COUNT(1),
95 .C_IMPLEMENTATION_TYPE(2),
96 .C_INIT_WR_PNTR_VAL(0),
98 .C_MIF_FILE_NAME("BlankString"),
100 .C_OPTIMIZATION_MODE(0),
102 .C_PRELOAD_LATENCY(0),
104 .C_PRIM_FIFO_TYPE("2kx18"),
105 .C_PROG_EMPTY_THRESH_ASSERT_VAL(4),
106 .C_PROG_EMPTY_THRESH_NEGATE_VAL(5),
107 .C_PROG_EMPTY_TYPE(0),
108 .C_PROG_FULL_THRESH_ASSERT_VAL(2047),
109 .C_PROG_FULL_THRESH_NEGATE_VAL(2046),
110 .C_PROG_FULL_TYPE(0),
111 .C_RD_DATA_COUNT_WIDTH(12),
114 .C_RD_PNTR_WIDTH(11),
118 .C_USE_EMBEDDED_REG(0),
119 .C_USE_FIFO16_FLAGS(0),
120 .C_USE_FWFT_DATA_COUNT(1),
123 .C_WR_DATA_COUNT_WIDTH(12),
126 .C_WR_PNTR_WIDTH(11),
127 .C_WR_RESPONSE_LATENCY(1))
138 .RD_DATA_COUNT(rd_data_count),
139 .WR_DATA_COUNT(wr_data_count),
144 .PROG_EMPTY_THRESH(),
145 .PROG_EMPTY_THRESH_ASSERT(),
146 .PROG_EMPTY_THRESH_NEGATE(),
148 .PROG_FULL_THRESH_ASSERT(),
149 .PROG_FULL_THRESH_NEGATE(),
166 // synthesis translate_on
168 // XST black box declaration
169 // box_type "black_box"
170 // synthesis attribute box_type of fifo_xlnx_2Kx36_2clk is "black_box"