git.gag.com Git - debian/gnuradio/blob - usrp2/fpga/control_lib/wb_sim.v

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   3 module wb_sim();
   4
   5    wire wb_clk, wb_rst;
   6    wire start;
   7
   8    reg  POR, aux_clk, clk_fpga;
   9
  10    initial POR = 1'b1;
  11    initial #103 POR = 1'b0;
  12
  13    initial aux_clk = 1'b0;
  14    always #25 aux_clk = ~aux_clk;
  15
  16    initial clk_fpga = 1'bx;
  17    initial #3007 clk_fpga = 1'b0;
  18    always #7 clk_fpga = ~clk_fpga;
  19
  20    initial begin
  21       $dumpfile("wb_sim.vcd");
  22       $dumpvars(0,wb_sim);
  23    end
  24
  25    initial #10000 $finish;
  26
  27    wire [15:0] rom_addr;
  28    wire [47:0] rom_data;
  29    wire [31:0] wb_dat;
  30    wire [15:0] wb_adr;
  31    wire        wb_cyc,wb_stb,wb_we,wb_ack;
  32    wire [3:0]  wb_sel;
  33
  34    wire [31:0] port_output;
  35
  36
  37    system_control system_control(.dsp_clk(dsp_clk),
  38                                  .reset_out(reset_out),
  39                                  .wb_clk_o(wb_clk),
  40                                  .wb_rst_o(wb_rst),
  41                                  .wb_rst_o_alt(wb_rst_o_alt),
  42                                  .start (start),
  43                                  .aux_clk(aux_clk),
  44                                  .clk_fpga(clk_fpga),
  45                                  .POR   (POR),
  46                                  .done  (done));
  47
  48    clock_bootstrap_rom cbrom(.addr(rom_addr),.data(rom_data));
  49
  50    wb_bus_writer bus_writer(.rom_addr   (rom_addr[15:0]),
  51                             .wb_dat_o   (wb_dat[31:0]),
  52                             .wb_adr_o   (wb_adr[15:0]),
  53                             .wb_cyc_o   (wb_cyc),
  54                             .wb_sel_o   (wb_sel[3:0]),
  55                             .wb_stb_o   (wb_stb),
  56                             .wb_we_o    (wb_we),
  57                             .start      (start),
  58                             .done       (done),
  59                             .rom_data   (rom_data[47:0]),
  60                             .wb_clk_i   (wb_clk),
  61                             .wb_rst_i   (wb_rst),
  62                             .wb_ack_i   (wb_ack));
  63
  64    wb_output_pins32 output_pins(.wb_dat_o(),
  65                                 .wb_ack_o(wb_ack),
  66                                 .port_output(port_output[31:0]),
  67                                 .wb_rst_i(wb_rst),
  68                                 .wb_clk_i(wb_clk),
  69                                 .wb_dat_i(wb_dat[31:0]),
  70                                 .wb_we_i(wb_we),
  71                                 .wb_sel_i(wb_sel[3:0]),
  72                                 .wb_stb_i(wb_stb),
  73                                 .wb_cyc_i(wb_cyc));
  74
  75
  76
  77
  78 endmodule // wb_sim
  79