3 // Note -- clocks must be synchronous (derived from the same source)
4 // Assumes alt_clk is running at a multiple of wb_clk
10 input [15:0] wb_adr_i,
11 output reg [31:0] wb_dat_o,
32 always @(posedge wb_clk_i)
36 wb_ack_o <= wb_stb_i & ~wb_ack_o;
38 always @(posedge wb_clk_i)
40 0 : wb_dat_o <= word00;
41 1 : wb_dat_o <= word01;
42 2 : wb_dat_o <= word02;
43 3 : wb_dat_o <= word03;
44 4 : wb_dat_o <= word04;
45 5 : wb_dat_o <= word05;
46 6 : wb_dat_o <= word06;
47 7 : wb_dat_o <= word07;
48 8 : wb_dat_o <= word08;
49 9 : wb_dat_o <= word09;
50 10: wb_dat_o <= word10;
51 11: wb_dat_o <= word11;
52 12: wb_dat_o <= word12;
53 13: wb_dat_o <= word13;
54 14: wb_dat_o <= word14;
55 15: wb_dat_o <= word15;
56 endcase // case(addr_reg[3:0])
58 endmodule // wb_readback_mux