3 // Since this is a block ram, there are no byte-selects and there is a 1-cycle read latency
4 // These have to be a multiple of 512 lines (2K) long
11 input [AWIDTH-1:0] adr_i,
13 output reg [31:0] dat_o,
16 reg [31:0] distram [0:1<<(AWIDTH-1)];
18 always @(posedge clk_i)
21 distram[adr_i] <= dat_i;
22 dat_o <= distram[adr_i];
26 always @(posedge clk_i)
29 always @(posedge clk_i)
32 assign ack_o = stb_i & (we_i | (stb_d1 & ~ack_d1));
33 endmodule // wb_ram_block