4 // WB Bus Master device to send a sequence of single-word transactions
5 // based on a list in a RAM or ROM (FASM interface)
6 // ROM data format is {WB_ADDR[15:0],WB_DATA[31:0]}
7 // continues until it gets an all-1s entry
9 module wb_bus_writer (input start,
11 output reg [15:0] rom_addr,
12 input [47:0] rom_data,
13 // WB Master Interface, don't need wb_dat_i
16 output [31:0] wb_dat_o,
18 output [15:0] wb_adr_o,
20 output [3:0] wb_sel_o,
30 assign done = (state != `IDLE) && (&rom_data); // Done when we see all 1s
32 always @(posedge wb_clk_i)
43 else if((state == `READ) && wb_ack_i)
47 rom_addr <= #1 rom_addr + 1;
49 assign wb_dat_o = rom_data[31:0];
50 assign wb_adr_o = rom_data[47:32];
51 assign wb_sel_o = 4'b1111; // All writes are the full 32 bits
53 assign wb_cyc_o = !done & (state != `IDLE);
54 assign wb_stb_o = !done & (state != `IDLE);
55 assign wb_we_o = !done & (state != `IDLE);
57 endmodule // wb_bus_writer