git.gag.com Git - debian/gnuradio/blob - usrp2/fpga/control_lib/system_control_tb.v

   1
   2
   3 module system_control_tb();
   4
   5    reg  aux_clk, clk_fpga;
   6    wire wb_clk, dsp_clk;
   7    wire wb_rst, dsp_rst, rl_rst, proc_rst;
   8
   9    reg  rl_done, clock_ready;
  10
  11    initial aux_clk = 1'b0;
  12    always #25 aux_clk = ~aux_clk;
  13
  14    initial clk_fpga = 1'b0;
  15
  16    initial clock_ready = 1'b0;
  17    initial
  18      begin
  19         @(negedge proc_rst);
  20         #1003 clock_ready <= 1'b1;
  21      end
  22
  23    always #7 clk_fpga = ~clk_fpga;
  24
  25    initial begin
  26       $dumpfile("system_control_tb.vcd");
  27       $dumpvars(0,system_control_tb);
  28    end
  29
  30    initial #10000 $finish;
  31
  32    initial
  33      begin
  34         @(negedge rl_rst);
  35         rl_done <= 1'b0;
  36         #1325 rl_done <= 1'b1;
  37      end
  38
  39    initial
  40      begin
  41         @(negedge proc_rst);
  42         clock_ready <= 1'b0;
  43         #327 clock_ready <= 1'b1;
  44      end
  45
  46    system_control
  47      system_control(.aux_clk_i(aux_clk),.clk_fpga_i(clk_fpga),
  48                     .dsp_clk_o(dsp_clk),.wb_clk_o(wb_clk),
  49                     .ram_loader_rst_o(rl_rst),
  50                     .processor_rst_o(proc_rst),
  51                     .wb_rst_o(wb_rst),
  52                     .dsp_rst_o(dsp_rst),
  53                     .ram_loader_done_i(rl_done),
  54                     .clock_ready_i(clock_ready),
  55                     .debug_o());
  56
  57 endmodule // system_control_tb