git.gag.com Git - debian/gnuradio/blob - usrp2/fpga/control_lib/system_control.v

   1 // System bootup order:
   2 //    0 - Internal POR to reset this block.  Maybe control it from CPLD in the future?
   3 //    1 - Everything in reset
   4 //    2 - Take RAM Loader out of reset
   5 //    3 - When RAM Loader done, take processor and wishbone out of reset
   6
   7 module system_control
   8   (input wb_clk_i,
   9    output reg ram_loader_rst_o,
  10    output reg wb_rst_o,
  11    input ram_loader_done_i
  12    );
  13
  14    reg          POR = 1'b1;
  15    reg [3:0]    POR_ctr;
  16
  17    initial POR_ctr = 4'd0;
  18    always @(posedge wb_clk_i)
  19      if(POR_ctr == 4'd15)
  20        POR <= 1'b0;
  21      else
  22        POR_ctr <= POR_ctr + 4'd1;
  23
  24    always @(posedge POR or posedge wb_clk_i)
  25      if(POR)
  26        ram_loader_rst_o <= 1'b1;
  27      else
  28        ram_loader_rst_o <= #1 1'b0;
  29
  30    // Main system reset
  31    reg          delayed_rst;
  32
  33    always @(posedge POR or posedge wb_clk_i)
  34      if(POR)
  35        begin
  36           wb_rst_o <= 1'b1;
  37           delayed_rst <= 1'b1;
  38        end
  39      else if(ram_loader_done_i)
  40        begin
  41           delayed_rst <= 1'b0;
  42           wb_rst_o <= delayed_rst;
  43        end
  44
  45 endmodule // system_control
  46
  47