5 input [7:0] fifo_in, input fifo_write, output [7:0] fifo_level, output fifo_full,
6 input [15:0] clkdiv, output baudclk, output reg tx);
12 wire [7:0] char_to_send;
14 medfifo #(.WIDTH(8),.DEPTH(DEPTH)) fifo
16 .datain(fifo_in),.write(fifo_write),.full(fifo_full),
17 .dataout(char_to_send),.read(read),.empty(empty),
18 .clear(0),.space(fifo_level),.occupied() );
23 else if (baud_ctr >= clkdiv)
26 baud_ctr <= baud_ctr + 1;
31 else if(baud_ctr == clkdiv)
35 bit_ctr <= bit_ctr + 1;
46 2 : tx <= char_to_send[0];
47 3 : tx <= char_to_send[1];
48 4 : tx <= char_to_send[2];
49 5 : tx <= char_to_send[3];
50 6 : tx <= char_to_send[4];
51 7 : tx <= char_to_send[5];
52 8 : tx <= char_to_send[6];
53 9 : tx <= char_to_send[7];
55 endcase // case(bit_ctr)
57 assign read = (bit_ctr == 9) && (baud_ctr == clkdiv);
58 assign baudclk = (baud_ctr == 1); // Only for debug purposes
60 endmodule // simple_uart_tx