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   1
   2 // Dual ported RAM for Harvard architecture processors
   3 //    Does no forwarding
   4 //    Addresses are byte-oriented, so botton 2 address bits are ignored.  FIXME
   5 //    AWIDTH of 13 gives 8K bytes.  For Spartan 3, if the total RAM size is not a
   6 //    multiple of 8K then BRAM space is wasted
   7
   8 module ram_wb_harvard #(parameter AWIDTH=13)
   9   (input wb_clk_i,
  10    input wb_rst_i,
  11
  12    input [AWIDTH-1:0] iwb_adr_i,
  13    input [31:0] iwb_dat_i,
  14    output reg [31:0] iwb_dat_o,
  15    input iwb_we_i,
  16    output reg iwb_ack_o,
  17    input iwb_stb_i,
  18    input [3:0] iwb_sel_i,
  19
  20    input [AWIDTH-1:0] dwb_adr_i,
  21    input [31:0] dwb_dat_i,
  22    output reg [31:0] dwb_dat_o,
  23    input dwb_we_i,
  24    output reg dwb_ack_o,
  25    input dwb_stb_i,
  26    input [3:0] dwb_sel_i);
  27
  28    reg [7:0]     ram0 [0:(1<<(AWIDTH-2))-1];
  29    reg [7:0]     ram1 [0:(1<<(AWIDTH-2))-1];
  30    reg [7:0]     ram2 [0:(1<<(AWIDTH-2))-1];
  31    reg [7:0]     ram3 [0:(1<<(AWIDTH-2))-1];
  32
  33    // Instruction Read Port
  34    always @(posedge wb_clk_i)
  35      iwb_ack_o <= iwb_stb_i & ~iwb_ack_o;
  36
  37    always @(posedge wb_clk_i)
  38      iwb_dat_o[31:24] <= ram3[iwb_adr_i[AWIDTH-1:2]];
  39    always @(posedge wb_clk_i)
  40      iwb_dat_o[23:16] <= ram2[iwb_adr_i[AWIDTH-1:2]];
  41    always @(posedge wb_clk_i)
  42      iwb_dat_o[15:8] <= ram1[iwb_adr_i[AWIDTH-1:2]];
  43    always @(posedge wb_clk_i)
  44      iwb_dat_o[7:0] <= ram0[iwb_adr_i[AWIDTH-1:2]];
  45
  46    always @(posedge wb_clk_i)
  47      if(iwb_we_i & iwb_stb_i & iwb_sel_i[3])
  48        ram3[iwb_adr_i[AWIDTH-1:2]] <= iwb_dat_i[31:24];
  49    always @(posedge wb_clk_i)
  50      if(iwb_we_i & iwb_stb_i & iwb_sel_i[2])
  51        ram2[iwb_adr_i[AWIDTH-1:2]] <= iwb_dat_i[23:16];
  52    always @(posedge wb_clk_i)
  53      if(iwb_we_i & iwb_stb_i & iwb_sel_i[1])
  54        ram1[iwb_adr_i[AWIDTH-1:2]] <= iwb_dat_i[15:8];
  55    always @(posedge wb_clk_i)
  56      if(iwb_we_i & iwb_stb_i & iwb_sel_i[0])
  57        ram0[iwb_adr_i[AWIDTH-1:2]] <= iwb_dat_i[7:0];
  58
  59    // Data Port
  60    always @(posedge wb_clk_i)
  61      dwb_ack_o <= dwb_stb_i & ~dwb_ack_o;
  62
  63    always @(posedge wb_clk_i)
  64      dwb_dat_o[31:24] <= ram3[dwb_adr_i[AWIDTH-1:2]];
  65    always @(posedge wb_clk_i)
  66      dwb_dat_o[23:16] <= ram2[dwb_adr_i[AWIDTH-1:2]];
  67    always @(posedge wb_clk_i)
  68      dwb_dat_o[15:8] <= ram1[dwb_adr_i[AWIDTH-1:2]];
  69    always @(posedge wb_clk_i)
  70      dwb_dat_o[7:0]  <= ram0[dwb_adr_i[AWIDTH-1:2]];
  71
  72    always @(posedge wb_clk_i)
  73      if(dwb_we_i & dwb_stb_i & dwb_sel_i[3])
  74        ram3[dwb_adr_i[AWIDTH-1:2]] <= dwb_dat_i[31:24];
  75    always @(posedge wb_clk_i)
  76      if(dwb_we_i & dwb_stb_i & dwb_sel_i[2])
  77        ram2[dwb_adr_i[AWIDTH-1:2]] <= dwb_dat_i[23:16];
  78    always @(posedge wb_clk_i)
  79      if(dwb_we_i & dwb_stb_i & dwb_sel_i[1])
  80        ram1[dwb_adr_i[AWIDTH-1:2]] <= dwb_dat_i[15:8];
  81    always @(posedge wb_clk_i)
  82      if(dwb_we_i & dwb_stb_i & dwb_sel_i[0])
  83        ram0[dwb_adr_i[AWIDTH-1:2]] <= dwb_dat_i[7:0];
  84
  85 endmodule // ram_wb_harvard
  86