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   1
   2 module fifo_short
   3   #(parameter WIDTH=32)
   4    (input clk, input reset, input clear,
   5     input [WIDTH-1:0] datain,
   6     input src_rdy_i,
   7     output dst_rdy_o,
   8     output [WIDTH-1:0] dataout,
   9     output src_rdy_o,
  10     input dst_rdy_i,
  11
  12     output reg [4:0] space,
  13     output reg [4:0] occupied);
  14
  15    reg full, empty;
  16    wire write        = src_rdy_i & dst_rdy_o;
  17    wire read         = dst_rdy_i & src_rdy_o;
  18
  19    assign dst_rdy_o  = ~full;
  20    assign src_rdy_o  = ~empty;
  21
  22    reg [3:0]      a;
  23    genvar         i;
  24
  25    generate
  26       for (i=0;i<WIDTH;i=i+1)
  27         begin : gen_srl16
  28            SRL16E
  29              srl16e(.Q(dataout[i]),
  30                     .A0(a[0]),.A1(a[1]),.A2(a[2]),.A3(a[3]),
  31                     .CE(write),.CLK(clk),.D(datain[i]));
  32         end
  33    endgenerate
  34
  35    always @(posedge clk)
  36      if(reset)
  37        begin
  38           a <= 0;
  39           empty <= 1;
  40           full <= 0;
  41        end
  42      else if(clear)
  43        begin
  44           a <= 0;
  45           empty <= 1;
  46           full<= 0;
  47        end
  48      else if(read & ~write)
  49        begin
  50           full <= 0;
  51           if(a==0)
  52             empty <= 1;
  53           else
  54             a <= a - 1;
  55        end
  56      else if(write & ~read)
  57        begin
  58           empty <= 0;
  59           if(~empty)
  60             a <= a + 1;
  61           if(a == 14)
  62             full <= 1;
  63        end
  64
  65    // NOTE will fail if you write into a full fifo or read from an empty one
  66
  67    //////////////////////////////////////////////////////////////
  68    // space and occupied are used for diagnostics, not
  69    // guaranteed correct
  70
  71    //assign space = full ? 0 : empty ? 16 : 15-a;
  72    //assign occupied = empty ? 0 : full ? 16 : a+1;
  73
  74    always @(posedge clk)
  75      if(reset)
  76        space <= 16;
  77      else if(clear)
  78        space <= 16;
  79      else if(read & ~write)
  80        space <= space + 1;
  81      else if(write & ~read)
  82        space <= space - 1;
  83
  84    always @(posedge clk)
  85      if(reset)
  86        occupied <= 0;
  87      else if(clear)
  88        occupied <= 0;
  89      else if(read & ~write)
  90        occupied <= occupied - 1;
  91      else if(write & ~read)
  92        occupied <= occupied + 1;
  93
  94 endmodule // fifo_short
  95