3 (input clk, input reset, input clear,
8 output reg [7:0] ll_data,
16 wire ll_sof, ll_eof, ll_src_rdy;
17 assign ll_sof_n = ~ll_sof;
18 assign ll_eof_n = ~ll_eof;
19 assign ll_src_rdy_n = ~ll_src_rdy;
20 wire ll_dst_rdy = ~ll_dst_rdy_n;
22 wire f36_sof = f36_data[32];
23 wire f36_eof = f36_data[33];
24 wire f36_occ = f36_data[35:34];
25 wire advance, end_early;
27 assign debug = {29'b0,state};
41 0 : ll_data = f36_data[31:24];
42 1 : ll_data = f36_data[23:16];
43 2 : ll_data = f36_data[15:8];
44 3 : ll_data = f36_data[7:0];
45 default : ll_data = f36_data[31:24];
46 endcase // case (state)
48 assign ll_sof = (state==0) & f36_sof;
49 assign ll_eof = f36_eof & (((state==0)&(f36_occ==1)) |
50 ((state==1)&(f36_occ==2)) |
51 ((state==2)&(f36_occ==3)) |
54 assign ll_src_rdy = f36_src_rdy_i;
56 assign advance = ll_src_rdy & ll_dst_rdy;
57 assign f36_dst_rdy_o = advance & ((state==3)|ll_eof);
60 endmodule // ll8_to_fifo36