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   1
   2 module fifo19_to_fifo36
   3   (input clk, input reset, input clear,
   4    input [18:0] f19_datain,
   5    input f19_src_rdy_i,
   6    output f19_dst_rdy_o,
   7
   8    output [35:0] f36_dataout,
   9    output f36_src_rdy_o,
  10    input f36_dst_rdy_i
  11    );
  12
  13    reg   f36_sof, f36_eof, f36_occ;
  14
  15    reg [1:0] state;
  16    reg [15:0] dat0, dat1;
  17
  18    wire f19_sof  = f19_datain[16];
  19    wire f19_eof  = f19_datain[17];
  20    wire f19_occ  = f19_datain[18];
  21
  22    wire xfer_out = f36_src_rdy_o & f36_dst_rdy_i;
  23
  24    always @(posedge clk)
  25      if(f19_src_rdy_i & ((state==0)|xfer_out))
  26        f36_sof  <= f19_sof;
  27
  28    always @(posedge clk)
  29      if(f19_src_rdy_i & ((state != 2)|xfer_out))
  30        f36_eof  <= f19_eof;
  31
  32    always @(posedge clk)    // FIXME check this
  33      if(f19_eof)
  34        f36_occ  <= {state[0],f19_occ};
  35      else
  36        f36_occ  <= 0;
  37
  38    always @(posedge clk)
  39      if(reset)
  40        state    <= 0;
  41      else
  42        if(f19_src_rdy_i)
  43          case(state)
  44            0 :
  45              if(f19_eof)
  46                state <= 2;
  47              else
  48                state <= 1;
  49            1 :
  50              state <= 2;
  51            2 :
  52              if(xfer_out)
  53                state       <= 1;
  54          endcase // case(state)
  55        else
  56          if(xfer_out)
  57            state           <= 0;
  58
  59    always @(posedge clk)
  60      if(f19_src_rdy_i & (state==1))
  61        dat1                <= f19_datain;
  62
  63    always @(posedge clk)
  64      if(f19_src_rdy_i & ((state==0) | xfer_out))
  65        dat0                <= f19_datain;
  66
  67    assign    f19_dst_rdy_o  = xfer_out | (state != 2);
  68    assign    f36_dataout    = {f36_occ,f36_eof,f36_sof,dat0,dat1};
  69    assign    f36_src_rdy_o  = (state == 2);
  70
  71 endmodule // fifo19_to_fifo36