2 module cascadefifo_2clock
3 #(parameter DWIDTH=32, AWIDTH=9)
4 (input wclk, input [DWIDTH-1:0] datain, input src_rdy_i, output dst_rdy_o, output [AWIDTH-1:0] level_wclk,
5 input rclk, output [DWIDTH-1:0] dataout, output src_rdy_o, input dst_rdy_i, output [AWIDTH-1:0] level_rclk,
8 wire [DWIDTH-1:0] data_int1, data_int2;
9 wire src_rdy_int1, src_rdy_int2, dst_rdy_int1, dst_rdy_int2;
11 fifo_short #(.WIDTH(DWIDTH)) shortfifo
12 (.clk(wclk), .reset(arst), .clear(0),
13 .datain(datain), .src_rdy_i(src_rdy_i), .dst_rdy_o(dst_rdy_o),
14 .dataout(data_int1), .src_rdy_o(src_rdy_int1), .dst_rdy_i(dst_rdy_int1) );
16 newfifo_2clock #(.DWIDTH(DWIDTH),.AWIDTH(AWIDTH)) fifo_2clock
17 (.wclk(wclk), .datain(data_int1), .src_rdy_i(src_rdy_int1), .dst_rdy_o(dst_rdy_int1), .level_wclk(level_wclk),
18 .rclk(rclk), .dataout(data_int2), .src_rdy_o(src_rdy_int2), .dst_rdy_i(dst_rdy_int2), .level_rclk(level_rclk),
21 fifo_short #(.WIDTH(DWIDTH)) shortfifo2
22 (.clk(rclk), .reset(arst), .clear(0),
23 .datain(data_int2), .src_rdy_i(src_rdy_int2), .dst_rdy_o(dst_rdy_int2),
24 .dataout(dataout), .src_rdy_o(src_rdy_o), .dst_rdy_i(dst_rdy_i) );
26 endmodule // fifo_2clock_casc