7 input [WIDTH-1:0] datain,
8 output [WIDTH-1:0] dataout,
15 output [15:0] occupied,
19 output reg [18:0] RAM_A,
28 wire [4:0] path1_occ, path2_space;
29 wire [35:0] path1_dat, path2_dat;
31 shortfifo #(.WIDTH(WIDTH)) sf1
32 (.clk(clk),.rst(rst),.clear(clear),
33 .datain(datain),.write(write),.full(full),
34 .dataout(path1_dat),.read(path1_read),.empty(path1_empty),
35 .space(),.occupied(path1_occ) );
36 wire path1_almost_empty = (path1_occ == 5'd1);
38 shortfifo #(.WIDTH(WIDTH)) sf2
39 (.clk(clk),.rst(rst),.clear(clear),
40 .datain(path2_dat),.write(path2_write),.full(path2_full),
41 .dataout(dataout),.read(read),.empty(empty),
42 .space(path2_space),.occupied() );
43 wire path2_almost_full = (path2_space == 5'd1);
45 assign RAM_CE1n = 1'b0;
46 assign RAM_CENn = 1'b0;
49 assign RAM_LDn = 1'b0;
52 wire write_now, read_now, idle, phase;
53 reg ram_full, ram_empty;
55 reg [17:0] read_ptr, write_ptr;
58 localparam ZBT_IDLE = 0;
59 localparam ZBT_WRITE_UPPER = 2;
60 localparam ZBT_WRITE_LOWER = 3;
61 localparam ZBT_READ_UPPER = 4;
62 localparam ZBT_READ_LOWER = 5;
64 wire can_write = ~ram_full & ~path1_empty;
65 wire can_write_chain = can_write & ~path1_almost_empty;
67 wire can_read = ~ram_empty & ~path2_full;
68 wire can_read_chain = can_read & ~path2_almost_full;
70 assign phase = zbt_state[0];
72 reg [17:0] ram_occupied;
73 wire ram_almost_empty = (write_ptr == (read_ptr+1'b1));
74 wire ram_almost_full = ((write_ptr+1'b1) == read_ptr);
79 zbt_state <= ZBT_IDLE;
90 zbt_state <= ZBT_READ_UPPER;
92 zbt_state <= ZBT_WRITE_UPPER;
96 zbt_state <= ZBT_WRITE_LOWER;
97 ram_occupied <= ram_occupied + 1;
99 if(ram_occupied == 18'd10)
104 write_ptr <= write_ptr + 1;
106 zbt_state <= ZBT_READ_UPPER;
107 else if(can_write_chain)
108 zbt_state <= ZBT_WRITE_UPPER;
110 zbt_state <= ZBT_IDLE;
114 zbt_state <= ZBT_READ_LOWER;
115 ram_occupied <= ram_occupied - 1;
117 if(ram_occupied == 18'd1)
122 read_ptr <= read_ptr + 1;
124 zbt_state <= ZBT_READ_UPPER;
125 else if(can_write_chain)
126 zbt_state <= ZBT_WRITE_UPPER;
128 zbt_state <= ZBT_IDLE;
131 zbt_state <= ZBT_IDLE;
132 endcase // case(zbt_state)
134 // Need to generate RAM_WEn, RAM_OEn, RAM_D, RAM_A;
135 assign path1_read = (zbt_state == ZBT_WRITE_LOWER);
136 reg path2_write, delayed_read_upper, delayed_read_lower, delayed_write;
138 always @(posedge clk)
139 if(delayed_read_upper)
140 path2_dat[35:18] <= RAM_D;
141 always @(posedge clk)
142 if(delayed_read_lower)
143 path2_dat[17:0] <= RAM_D;
145 always @(posedge clk)
148 delayed_read_upper <= 0;
149 delayed_read_lower <= 0;
154 delayed_read_upper <= (zbt_state == ZBT_READ_LOWER);
155 delayed_read_lower <= delayed_read_upper;
156 path2_write <= delayed_read_lower;
159 reg [17:0] RAM_D_pre2, RAM_D_pre1, RAM_D_out;
161 always @(posedge clk)
162 RAM_D_pre2 <= phase ? path1_dat[17:0] : path1_dat[35:18];
164 always @(posedge clk) RAM_D_pre1 <= RAM_D_pre2;
165 always @(posedge clk) RAM_D_out <= RAM_D_pre1;
166 reg wr_del_1, wr_del_2;
167 always @(posedge clk)
176 delayed_write <= wr_del_2;
177 wr_del_2 <= wr_del_1;
178 wr_del_1 <= write_now;
181 reg delayed_read, rd_del_1, rd_del_2;
182 always @(posedge clk)
191 delayed_read <= rd_del_2;
192 rd_del_2 <= rd_del_1;
193 rd_del_1 <= read_now;
196 assign RAM_D = delayed_write ? RAM_D_out : 18'bzzzzzzzzzzzzzzzzzz;
197 assign write_now = (zbt_state == ZBT_WRITE_UPPER) || (zbt_state == ZBT_WRITE_LOWER);
198 assign read_now = (zbt_state == ZBT_READ_UPPER) || (zbt_state == ZBT_READ_LOWER);
200 always @(posedge clk)
201 RAM_A <= write_now ? {write_ptr,phase} : {read_ptr,phase};
203 always @(posedge clk)
204 RAM_WEn <= ~write_now;
206 assign RAM_OEn = ~delayed_read;
209 endmodule // giantfifo