git.gag.com Git - debian/gnuradio/blob - usrp2/fpga/control_lib/fifo_tb.v

   1 module fifo_tb();
   2
   3    reg clk, rst;
   4    wire short_full, short_empty, long_full, long_empty;
   5    wire casc_full, casc_empty, casc2_full, casc2_empty;
   6    reg  read, write;
   7
   8    wire [7:0] short_do, long_do;
   9    wire [7:0] casc_do, casc2_do;
  10    reg [7:0]  di;
  11
  12    reg        clear = 0;
  13
  14    shortfifo #(.WIDTH(8)) shortfifo
  15      (.clk(clk),.rst(rst),.datain(di),.dataout(short_do),.clear(clear),
  16       .read(read),.write(write),.full(short_full),.empty(short_empty));
  17
  18    longfifo #(.WIDTH(8), .SIZE(4)) longfifo
  19      (.clk(clk),.rst(rst),.datain(di),.dataout(long_do),.clear(clear),
  20       .read(read),.write(write),.full(long_full),.empty(long_empty));
  21
  22    cascadefifo #(.WIDTH(8), .SIZE(4)) cascadefifo
  23      (.clk(clk),.rst(rst),.datain(di),.dataout(casc_do),.clear(clear),
  24       .read(read),.write(write),.full(casc_full),.empty(casc_empty));
  25
  26    cascadefifo2 #(.WIDTH(8), .SIZE(4)) cascadefifo2
  27      (.clk(clk),.rst(rst),.datain(di),.dataout(casc2_do),.clear(clear),
  28       .read(read),.write(write),.full(casc2_full),.empty(casc2_empty));
  29
  30    initial rst = 1;
  31    initial #1000 rst = 0;
  32    initial clk = 0;
  33    always #50 clk = ~clk;
  34
  35    initial di = 8'hAE;
  36    initial read = 0;
  37    initial write = 0;
  38
  39    always @(posedge clk)
  40      if(write)
  41        di <= di + 1;
  42
  43    always @(posedge clk)
  44      begin
  45         if(short_full != long_full)
  46           $display("Error: FULL mismatch");
  47         if(short_empty != long_empty)
  48           $display("Note: EMPTY mismatch, usually not a problem (longfifo has 2 cycle latency)");
  49         if(read & (short_do != long_do))
  50           $display("Error: DATA mismatch");
  51      end
  52
  53    initial $dumpfile("fifo_tb.vcd");
  54    initial $dumpvars(0,fifo_tb);
  55
  56    initial
  57      begin
  58         @(negedge rst);
  59         @(posedge clk);
  60         repeat (10)
  61           @(posedge clk);
  62         write <= 1;
  63         @(posedge clk);
  64         write <= 0;
  65         @(posedge clk);
  66         @(posedge clk);
  67         @(posedge clk);
  68         @(posedge clk);
  69         @(posedge clk);
  70         @(posedge clk);
  71         @(posedge clk);
  72         @(posedge clk);
  73         read <= 1;
  74         @(posedge clk);
  75         read <= 0;
  76         @(posedge clk);
  77         @(posedge clk);
  78         @(posedge clk);
  79         @(posedge clk);
  80         @(posedge clk);
  81
  82         repeat(10)
  83           begin
  84              write <= 1;
  85              @(posedge clk);
  86              write <= 0;
  87              @(posedge clk);
  88              @(posedge clk);
  89              @(posedge clk);
  90              read <= 1;
  91              @(posedge clk);
  92              read <= 0;
  93              @(posedge clk);
  94              @(posedge clk);
  95              @(posedge clk);
  96              @(posedge clk);
  97              @(posedge clk);
  98           end // repeat (10)
  99
 100         write <= 1;
 101         repeat (4)
 102           @(posedge clk);
 103         write <= 0;
 104         @(posedge clk);
 105         read <= 1;
 106         repeat (4)
 107           @(posedge clk);
 108         read <= 0;
 109         @(posedge clk);
 110
 111
 112         write <= 1;
 113         repeat (4)
 114           @(posedge clk);
 115         write <= 0;
 116         @(posedge clk);
 117         repeat (4)
 118           begin
 119              read <= 1;
 120              @(posedge clk);
 121              read <= 0;
 122              @(posedge clk);
 123           end
 124
 125         write <= 1;
 126         @(posedge clk);
 127         @(posedge clk);
 128         @(posedge clk);
 129         @(posedge clk);
 130         read <= 1;
 131         repeat (5)
 132           @(posedge clk);
 133         write <= 0;
 134           @(posedge clk);
 135           @(posedge clk);
 136         read <= 0;
 137         @(posedge clk);
 138
 139         write <= 1;
 140         repeat (16)
 141           @(posedge clk);
 142         write <= 0;
 143         @(posedge clk);
 144
 145         read <= 1;
 146         repeat (16)
 147           @(posedge clk);
 148         read <= 0;
 149         @(posedge clk);
 150
 151         repeat (10)
 152           @(posedge clk);
 153         $finish;
 154      end
 155 endmodule // longfifo_tb