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   1
   2 // Dual ported RAM
   3 //    Addresses are byte-oriented, so botton 2 address bits are ignored.
   4 //    AWIDTH of 13 allows you to address 8K bytes.
   5 //    For Spartan 3, if the total RAM size is not a multiple of 8K then BRAM space is wasted
   6 // RAM_SIZE parameter allows odd-sized RAMs, like 24K
   7
   8 module dpram32 #(parameter AWIDTH=15,
   9                  parameter RAM_SIZE=16384)
  10   (input clk,
  11
  12    input [AWIDTH-1:0] adr1_i,
  13    input [31:0] dat1_i,
  14    output reg [31:0] dat1_o,
  15    input we1_i,
  16    input en1_i,
  17    input [3:0] sel1_i,
  18
  19    input [AWIDTH-1:0] adr2_i,
  20    input [31:0] dat2_i,
  21    output reg [31:0] dat2_o,
  22    input we2_i,
  23    input en2_i,
  24    input [3:0] sel2_i );
  25
  26    reg [7:0]   ram0 [0:(RAM_SIZE/4)-1];
  27    reg [7:0]   ram1 [0:(RAM_SIZE/4)-1];
  28    reg [7:0]   ram2 [0:(RAM_SIZE/4)-1];
  29    reg [7:0]   ram3 [0:(RAM_SIZE/4)-1];
  30
  31    //  This is how we used to size the RAM -->
  32    //      reg [7:0]   ram3 [0:(1<<(AWIDTH-2))-1];
  33
  34    // Port 1
  35    always @(posedge clk)
  36      if(en1_i) dat1_o[31:24] <= ram3[adr1_i[AWIDTH-1:2]];
  37    always @(posedge clk)
  38      if(en1_i) dat1_o[23:16] <= ram2[adr1_i[AWIDTH-1:2]];
  39    always @(posedge clk)
  40      if(en1_i) dat1_o[15:8] <= ram1[adr1_i[AWIDTH-1:2]];
  41    always @(posedge clk)
  42      if(en1_i) dat1_o[7:0] <= ram0[adr1_i[AWIDTH-1:2]];
  43
  44    always @(posedge clk)
  45      if(we1_i & en1_i & sel1_i[3])
  46        ram3[adr1_i[AWIDTH-1:2]] <= dat1_i[31:24];
  47    always @(posedge clk)
  48      if(we1_i & en1_i & sel1_i[2])
  49        ram2[adr1_i[AWIDTH-1:2]] <= dat1_i[23:16];
  50    always @(posedge clk)
  51      if(we1_i & en1_i & sel1_i[1])
  52        ram1[adr1_i[AWIDTH-1:2]] <= dat1_i[15:8];
  53    always @(posedge clk)
  54      if(we1_i & en1_i & sel1_i[0])
  55        ram0[adr1_i[AWIDTH-1:2]] <= dat1_i[7:0];
  56
  57    // Port 2
  58    always @(posedge clk)
  59      if(en2_i) dat2_o[31:24] <= ram3[adr2_i[AWIDTH-1:2]];
  60    always @(posedge clk)
  61      if(en2_i) dat2_o[23:16] <= ram2[adr2_i[AWIDTH-1:2]];
  62    always @(posedge clk)
  63      if(en2_i) dat2_o[15:8] <= ram1[adr2_i[AWIDTH-1:2]];
  64    always @(posedge clk)
  65      if(en2_i) dat2_o[7:0] <= ram0[adr2_i[AWIDTH-1:2]];
  66
  67    always @(posedge clk)
  68      if(we2_i & en2_i & sel2_i[3])
  69        ram3[adr2_i[AWIDTH-1:2]] <= dat2_i[31:24];
  70    always @(posedge clk)
  71      if(we2_i & en2_i & sel2_i[2])
  72        ram2[adr2_i[AWIDTH-1:2]] <= dat2_i[23:16];
  73    always @(posedge clk)
  74      if(we2_i & en2_i & sel2_i[1])
  75        ram1[adr2_i[AWIDTH-1:2]] <= dat2_i[15:8];
  76    always @(posedge clk)
  77      if(we2_i & en2_i & sel2_i[0])
  78        ram0[adr2_i[AWIDTH-1:2]] <= dat2_i[7:0];
  79
  80 endmodule // dpram32
  81
  82