3 // Addresses are byte-oriented, so botton 2 address bits are ignored.
4 // AWIDTH of 13 allows you to address 8K bytes.
5 // For Spartan 3, if the total RAM size is not a multiple of 8K then BRAM space is wasted
6 // RAM_SIZE parameter allows odd-sized RAMs, like 24K
8 module dpram32 #(parameter AWIDTH=15,
9 parameter RAM_SIZE=16384)
12 input [AWIDTH-1:0] adr1_i,
14 output reg [31:0] dat1_o,
19 input [AWIDTH-1:0] adr2_i,
21 output reg [31:0] dat2_o,
26 reg [7:0] ram0 [0:(RAM_SIZE/4)-1];
27 reg [7:0] ram1 [0:(RAM_SIZE/4)-1];
28 reg [7:0] ram2 [0:(RAM_SIZE/4)-1];
29 reg [7:0] ram3 [0:(RAM_SIZE/4)-1];
31 // This is how we used to size the RAM -->
32 // reg [7:0] ram3 [0:(1<<(AWIDTH-2))-1];
36 if(en1_i) dat1_o[31:24] <= ram3[adr1_i[AWIDTH-1:2]];
38 if(en1_i) dat1_o[23:16] <= ram2[adr1_i[AWIDTH-1:2]];
40 if(en1_i) dat1_o[15:8] <= ram1[adr1_i[AWIDTH-1:2]];
42 if(en1_i) dat1_o[7:0] <= ram0[adr1_i[AWIDTH-1:2]];
45 if(we1_i & en1_i & sel1_i[3])
46 ram3[adr1_i[AWIDTH-1:2]] <= dat1_i[31:24];
48 if(we1_i & en1_i & sel1_i[2])
49 ram2[adr1_i[AWIDTH-1:2]] <= dat1_i[23:16];
51 if(we1_i & en1_i & sel1_i[1])
52 ram1[adr1_i[AWIDTH-1:2]] <= dat1_i[15:8];
54 if(we1_i & en1_i & sel1_i[0])
55 ram0[adr1_i[AWIDTH-1:2]] <= dat1_i[7:0];
59 if(en2_i) dat2_o[31:24] <= ram3[adr2_i[AWIDTH-1:2]];
61 if(en2_i) dat2_o[23:16] <= ram2[adr2_i[AWIDTH-1:2]];
63 if(en2_i) dat2_o[15:8] <= ram1[adr2_i[AWIDTH-1:2]];
65 if(en2_i) dat2_o[7:0] <= ram0[adr2_i[AWIDTH-1:2]];
68 if(we2_i & en2_i & sel2_i[3])
69 ram3[adr2_i[AWIDTH-1:2]] <= dat2_i[31:24];
71 if(we2_i & en2_i & sel2_i[2])
72 ram2[adr2_i[AWIDTH-1:2]] <= dat2_i[23:16];
74 if(we2_i & en2_i & sel2_i[1])
75 ram1[adr2_i[AWIDTH-1:2]] <= dat2_i[15:8];
77 if(we2_i & en2_i & sel2_i[0])
78 ram0[adr2_i[AWIDTH-1:2]] <= dat2_i[7:0];