3 // This FIFO exists to provide an intermediate point for the data on its
4 // long trek from one RAM (in the buffer pool) to another (in the longfifo)
5 // The shortfifo is more flexible in its placement since it is based on
7 // This one should only be used on transmit side applications. I.e. tx_mac, tx_dsp, etc.
8 // Spartan 3's have slow routing....
9 // If we REALLY need to, we could also do this on the output side,
10 // with for the receive side stuff
13 #(parameter WIDTH=32, SIZE=9)
14 (input clk, input rst,
15 input [WIDTH-1:0] datain,
16 output [WIDTH-1:0] dataout,
23 output [15:0] occupied);
25 wire [WIDTH-1:0] data_int;
26 wire empty_int, full_int, transfer;
27 wire [4:0] short_space, short_occupied;
28 wire [15:0] long_space, long_occupied;
30 shortfifo #(.WIDTH(WIDTH)) shortfifo
31 (.clk(clk),.rst(rst),.clear(clear),
32 .datain(datain), .write(write), .full(full),
33 .dataout(data_int), .read(transfer), .empty(empty_int),
34 .space(short_space),.occupied(short_occupied) );
36 longfifo #(.WIDTH(WIDTH),.SIZE(SIZE)) longfifo
37 (.clk(clk),.rst(rst),.clear(clear),
38 .datain(data_int), .write(transfer), .full(full_int),
39 .dataout(dataout), .read(read), .empty(empty),
40 .space(long_space),.occupied(long_occupied) );
42 assign transfer = ~empty_int & ~full_int;
44 assign space = {11'b0,short_space} + long_space;
45 assign occupied = {11'b0,short_occupied} + long_occupied;
47 endmodule // cascadefifo