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   1
   2 module buffer_int_tb ();
   3
   4    reg clk = 0;
   5    reg rst = 1;
   6
   7    initial #100 rst = 0;
   8    always #5 clk = ~clk;
   9
  10    wire en, we;
  11    wire [8:0] addr;
  12    wire [31:0] fifo2buf, buf2fifo;
  13
  14    wire [31:0] rd_dat_o;
  15    wire        rd_sop_o, rd_eop_o;
  16    reg         rd_done_i = 0, rd_error_i = 0, rd_read_i = 0;
  17
  18    reg [31:0]  wr_dat_i = 0;
  19    reg         wr_write_i=0, wr_done_i = 0, wr_error_i = 0;
  20    wire        wr_ready_o, wr_full_o;
  21
  22    reg         clear = 0, write = 0, read = 0;
  23    reg [8:0]   firstline = 0, lastline = 0;
  24    wire [3:0]  step = 1;
  25    wire [31:0] ctrl_word = {4'b0,3'b0,clear,write,read,step,lastline,firstline};
  26    reg         go = 0;
  27    wire        done, error;
  28
  29    buffer_int buffer_int
  30      (.clk(clk),.rst(rst),
  31       .ctrl_word(ctrl_word),.go(go),
  32       .done(done),.error(error),
  33
  34       // Buffer Interface
  35       .en_o(en),.we_o(we),.addr_o(addr),
  36       .dat_to_buf(fifo2buf),.dat_from_buf(buf2fifo),
  37
  38       // Write FIFO Interface
  39       .wr_dat_i(wr_dat_i), .wr_write_i(wr_write_i), .wr_done_i(wr_done_i), .wr_error_i(wr_error_i),
  40       .wr_ready_o(wr_ready_o), .wr_full_o(wr_full_o),
  41
  42       // Read FIFO Interface
  43       .rd_dat_o(rd_dat_o), .rd_read_i(rd_read_i), .rd_done_i(rd_done_i), .rd_error_i(rd_error_i),
  44       .rd_sop_o(rd_sop_o), .rd_eop_o(rd_eop_o)
  45       );
  46
  47    reg         ram_en = 0, ram_we = 0;
  48    reg [8:0]   ram_addr = 0;
  49    reg [31:0]  ram_data = 0;
  50
  51    ram_2port #(.DWIDTH(32),.AWIDTH(9)) ram_2port
  52      (.clka(clk), .ena(ram_en), .wea(ram_we), .addra(ram_addr), .dia(ram_data), .doa(),
  53       .clkb(clk), .enb(en), .web(we), .addrb(addr), .dib(fifo2buf), .dob(buf2fifo) );
  54
  55    initial
  56      begin
  57         @(negedge rst);
  58         @(posedge clk);
  59         FillRAM;
  60
  61         ResetBuffer;
  62         SetBufferRead(5,10);
  63         $display("Testing full read, no wait states.");
  64         while(!rd_sop_o)
  65           @(posedge clk);
  66         ReadLines(6,0);
  67         repeat (10)
  68           @(posedge clk);
  69
  70         ResetBuffer;
  71         SetBufferRead(5,10);
  72         $display("Testing full read, 2 wait states.");
  73         while(!rd_sop_o)
  74           @(posedge clk);
  75         ReadLines(6,2);
  76         repeat (10)
  77           @(posedge clk);
  78
  79         ResetBuffer;
  80         SetBufferRead(5,10);
  81         $display("Testing full read, done ON the last.");
  82         while(!rd_sop_o)
  83           @(posedge clk);
  84         ReadLines(5,2);
  85         rd_done_i <= 1;
  86         ReadALine;
  87         rd_done_i <= 0;
  88         repeat (10)
  89           @(posedge clk);
  90
  91         ResetBuffer;
  92         SetBufferRead(5,10);
  93         $display("Testing partial read, 0 wait states, then nothing after last.");
  94         while(!rd_sop_o)
  95           @(posedge clk);
  96         ReadLines(3,0);
  97         repeat (10)
  98           @(posedge clk);
  99
 100         ResetBuffer;
 101         SetBufferRead(5,10);
 102         $display("Testing partial read, 0 wait states, then done after last.");
 103         while(!rd_sop_o)
 104           @(posedge clk);
 105         ReadLines(3,0);
 106         rd_done_i <= 1;
 107         @(posedge clk);
 108         rd_done_i <= 0;
 109         repeat (10)
 110           @(posedge clk);
 111
 112         ResetBuffer;
 113         SetBufferRead(5,10);
 114         $display("Testing partial read, 0 wait states, then done at same time as last.");
 115         while(!rd_sop_o)
 116           @(posedge clk);
 117         ReadLines(2,0);
 118         rd_done_i <= 1;
 119         ReadALine;
 120         rd_done_i <= 0;
 121         repeat (10)
 122           @(posedge clk);
 123
 124         ResetBuffer;
 125         SetBufferRead(5,10);
 126         $display("Testing partial read, 3 wait states, then error at same time as last.");
 127         while(!rd_sop_o)
 128           @(posedge clk);
 129         ReadLines(2,3);
 130         rd_error_i <= 1;
 131         ReadALine;
 132         rd_error_i <= 0;
 133         repeat (10)
 134           @(posedge clk);
 135
 136         ResetBuffer;
 137         SetBufferRead(5,10);
 138         $display("Testing Reading too much, 3 wait states.");
 139         while(!rd_sop_o)
 140           @(posedge clk);
 141         ReadLines(9,3);
 142         repeat (10)
 143           @(posedge clk);
 144
 145         ResetBuffer;
 146         SetBufferRead(500,511);
 147         $display("Testing full read, to the end of the buffer.");
 148         while(!rd_sop_o)
 149           @(posedge clk);
 150         ReadLines(12,0);
 151         repeat (10)
 152           @(posedge clk);
 153
 154         ResetBuffer;
 155         SetBufferRead(0,511);
 156         $display("Testing full read, start to end of the buffer.");
 157         while(!rd_sop_o)
 158           @(posedge clk);
 159         ReadLines(512,0);
 160         repeat (10)
 161           @(posedge clk);
 162
 163         ResetBuffer;
 164         SetBufferRead(505,3);
 165         $display("Testing full read, wraparound");
 166         while(!rd_sop_o)
 167           @(posedge clk);
 168         ReadLines(11,0);
 169         repeat (10)
 170           @(posedge clk);
 171
 172         ResetBuffer;
 173         SetBufferWrite(10,15);
 174         $display("Testing Full Write, no wait states");
 175         while(!wr_ready_o)
 176           @(posedge clk);
 177         WriteLines(6,0,72);
 178         repeat (10)
 179           @(posedge clk);
 180
 181         ResetBuffer;
 182         SetBufferWrite(18,23);
 183         $display("Testing Full Write, 1 wait states");
 184         while(!wr_ready_o)
 185           @(posedge clk);
 186         WriteLines(6,0,101);
 187         repeat (10)
 188           @(posedge clk);
 189
 190         ResetBuffer;
 191         SetBufferWrite(27,40);
 192         $display("Testing Partial Write, 0 wait states");
 193         while(!wr_ready_o)
 194           @(posedge clk);
 195         WriteLines(6,0,201);
 196         repeat (10)
 197           @(posedge clk);
 198
 199         ResetBuffer;
 200         SetBufferWrite(35,200);
 201         $display("Testing Partial Write, 0 wait states, then done");
 202         while(!wr_ready_o)
 203           @(posedge clk);
 204         WriteLines(6,0,301);
 205         wr_done_i <= 1;
 206         @(posedge clk);
 207         wr_done_i <= 0;
 208         repeat (10)
 209           @(posedge clk);
 210
 211         ResetBuffer;
 212         SetBufferWrite(45,200);
 213         $display("Testing Partial Write, 0 wait states, then done and write simultaneously");
 214         while(!wr_ready_o)
 215           @(posedge clk);
 216         WriteLines(6,0,301);
 217         wr_done_i <= 1;
 218         WriteALine(400);
 219         wr_done_i <= 0;
 220         repeat (10)
 221           @(posedge clk);
 222
 223         ResetBuffer;
 224         SetBufferWrite(55,200);
 225         $display("Testing Partial Write, 0 wait states, then error");
 226         while(!wr_ready_o)
 227           @(posedge clk);
 228         WriteLines(6,0,501);
 229         wr_error_i <= 1;
 230         @(posedge clk);
 231         wr_error_i <= 0;
 232         repeat (10)
 233           @(posedge clk);
 234
 235         ResetBuffer;
 236         SetBufferRead(0,82);
 237         $display("Testing read after all the writes");
 238         while(!rd_sop_o)
 239           @(posedge clk);
 240         ReadLines(83,0);
 241         repeat (10)
 242           @(posedge clk);
 243
 244         ResetBuffer;
 245         SetBufferWrite(508,4);
 246         $display("Testing wraparound write");
 247         while(!wr_ready_o)
 248           @(posedge clk);
 249         WriteLines(9,0,601);
 250         repeat (10)
 251           @(posedge clk);
 252
 253         ResetBuffer;
 254         SetBufferRead(506,10);
 255         $display("Reading wraparound write");
 256         while(!rd_sop_o)
 257           @(posedge clk);
 258         ReadLines(17,0);
 259         repeat (10)
 260           @(posedge clk);
 261
 262         ResetBuffer;
 263         SetBufferWrite(0,511);
 264         $display("Testing Whole Buffer write");
 265         while(!wr_ready_o)
 266           @(posedge clk);
 267         WriteLines(512,0,1000);
 268         repeat (10)
 269           @(posedge clk);
 270
 271         ResetBuffer;
 272         SetBufferRead(0,511);
 273         $display("Reading Whole Buffer write");
 274         while(!rd_sop_o)
 275           @(posedge clk);
 276         ReadLines(512,0);
 277         repeat (10)
 278           @(posedge clk);
 279
 280         ResetBuffer;
 281         SetBufferWrite(5,10);
 282         $display("Testing Write Too Many");
 283         while(!wr_ready_o)
 284           @(posedge clk);
 285         WriteLines(12,0,2000);
 286         repeat (10)
 287           @(posedge clk);
 288
 289         ResetBuffer;
 290         SetBufferRead(0,15);
 291         $display("Reading back Write Too Many");
 292         while(!rd_sop_o)
 293           @(posedge clk);
 294         ReadLines(16,0);
 295         repeat (10)
 296           @(posedge clk);
 297
 298         ResetBuffer;
 299         SetBufferWrite(15,20);
 300         $display("Testing Write One Less Than Full");
 301         while(!wr_ready_o)
 302           @(posedge clk);
 303         WriteLines(5,0,2000);
 304         repeat (10)
 305           @(posedge clk);
 306
 307         ResetBuffer;
 308         SetBufferRead(13,22);
 309         $display("Reading back Write One Less Than Full");
 310         while(!rd_sop_o)
 311           @(posedge clk);
 312         ReadLines(10,0);
 313         repeat (10)
 314           @(posedge clk);
 315
 316         ResetBuffer;
 317         repeat(100)
 318           @(posedge clk);
 319         $finish;
 320      end
 321
 322    always @(posedge clk)
 323      if(rd_read_i == 1'd1)
 324        $display("READ Buffer %d, rd_sop_o %d, rd_eop_o %d", rd_dat_o, rd_sop_o, rd_eop_o);
 325
 326    always @(posedge clk)
 327      if(wr_write_i == 1'd1)
 328        $display("WRITE Buffer %d,  wr_ready_o %d, wr_full_o %d", wr_dat_i, wr_ready_o, wr_full_o);
 329
 330    initial begin
 331       $dumpfile("buffer_int_tb.vcd");
 332       $dumpvars(0,buffer_int_tb);
 333    end
 334
 335    task FillRAM;
 336       begin
 337          ram_addr <= 0;
 338          ram_data <= 0;
 339          @(posedge clk);
 340          ram_en <= 1;
 341          ram_we <= 1;
 342          @(posedge clk);
 343          repeat (511)
 344            begin
 345               ram_addr <= ram_addr + 1;
 346               ram_data <= ram_data + 1;
 347               ram_en <= 1;
 348               ram_we <= 1;
 349               @(posedge clk);
 350            end
 351          ram_en <= 0;
 352          ram_we <= 0;
 353          @(posedge clk);
 354          $display("Filled the RAM");
 355       end
 356    endtask // FillRAM
 357
 358    task ResetBuffer;
 359       begin
 360          clear <= 1; read <= 0; write <= 0;
 361          go <= 1;
 362          @(posedge clk);
 363          go <= 0;
 364          @(posedge clk);
 365          $display("Buffer Reset");
 366       end
 367    endtask // ClearBuffer
 368
 369    task SetBufferWrite;
 370       input [8:0] start;
 371       input [8:0] stop;
 372       begin
 373          clear <= 0; read <= 0; write <= 1;
 374          firstline <= start;
 375          lastline <= stop;
 376          go <= 1;
 377          @(posedge clk);
 378          go <= 0;
 379          @(posedge clk);
 380          $display("Buffer Set for Write");
 381       end
 382    endtask // SetBufferWrite
 383
 384    task SetBufferRead;
 385       input [8:0] start;
 386       input [8:0] stop;
 387       begin
 388          clear <= 0; read <= 1; write <= 0;
 389          firstline <= start;
 390          lastline <= stop;
 391          go <= 1;
 392          @(posedge clk);
 393          go <= 0;
 394          @(posedge clk);
 395          $display("Buffer Set for Read");
 396       end
 397    endtask // SetBufferRead
 398
 399    task ReadALine;
 400       begin
 401          #1 rd_read_i <= 1;
 402          @(posedge clk);
 403          rd_read_i <= 0;
 404       end
 405    endtask // ReadALine
 406
 407    task ReadLines;
 408       input [9:0] lines;
 409       input [7:0] wait_states;
 410       begin
 411          $display("Read Lines: Number %d, Wait States %d",lines,wait_states);
 412          repeat (lines)
 413            begin
 414               ReadALine;
 415               repeat (wait_states)
 416                 @(posedge clk);
 417            end
 418       end
 419    endtask // ReadLines
 420
 421    task WriteALine;
 422       input [31:0] value;
 423       begin
 424          #1 wr_write_i <= 1;
 425          wr_dat_i <= value;
 426          @(posedge clk);
 427          wr_write_i <= 0;
 428       end
 429    endtask // WriteALine
 430
 431    task WriteLines;
 432       input [9:0] lines;
 433       input [7:0] wait_states;
 434       input [31:0] value;
 435       begin
 436          $display("Write Lines: Number %d, Wait States %d",lines,wait_states);
 437          repeat(lines)
 438            begin
 439               value <= value + 1;
 440               WriteALine(value);
 441               repeat(wait_states)
 442                 @(posedge clk);
 443            end
 444       end
 445    endtask // WriteLines
 446
 447 endmodule // buffer_int_tb