2 // Automatic transmit/receive switching of control pins to daughterboards
3 // Store everything in registers for now, but could use a RAM for more
4 // complex state machines in the future
7 (input clk_i, input rst_i,
8 input [5:0] adr_i, input [3:0] sel_i, input [31:0] dat_i, output reg [31:0] dat_o,
9 input we_i, input stb_i, input cyc_i, output reg ack_o,
10 input run_rx, input run_tx, input [31:0] master_time,
11 output [31:0] ctrl_lines);
14 reg [31:0] atr_ram [0:15]; // DP distributed RAM
17 always @(posedge clk_i)
18 if(we_i & stb_i & cyc_i)
21 atr_ram[adr_i[5:2]][31:24] <= dat_i[31:24];
23 atr_ram[adr_i[5:2]][23:16] <= dat_i[23:16];
25 atr_ram[adr_i[5:2]][15:8] <= dat_i[15:8];
27 atr_ram[adr_i[5:2]][7:0] <= dat_i[7:0];
28 end // if (we_i & stb_i & cyc_i)
30 always @(posedge clk_i)
31 dat_o <= atr_ram[adr_i[5:2]];
33 always @(posedge clk_i)
34 ack_o <= stb_i & cyc_i & ~ack_o;
36 // Control side of DP RAM
37 assign ctrl_lines = atr_ram[state];
39 // Put a more complex state machine with time delays and multiple states here
40 // if daughterboard requires more complex sequencing
41 localparam ATR_IDLE = 4'd0;
42 localparam ATR_TX = 4'd1;
43 localparam ATR_RX = 4'd2;
44 localparam ATR_FULL_DUPLEX = 4'd3;
46 always @(posedge clk_i)
50 case ({run_rx,run_tx})
51 2'b00 : state <= ATR_IDLE;
52 2'b01 : state <= ATR_TX;
53 2'b10 : state <= ATR_RX;
54 2'b11 : state <= ATR_FULL_DUPLEX;
55 endcase // case({run_rx,run_tx})
57 endmodule // atr_controller