3 *-11.026821 2450 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
5 system_control_tb.aux_clk
7 system_control_tb.clk_fpga
9 system_control_tb.dsp_clk
10 system_control_tb.dsp_rst
11 system_control_tb.proc_rst
12 system_control_tb.rl_done
13 system_control_tb.rl_rst
14 system_control_tb.wb_clk
15 system_control_tb.wb_rst
16 system_control_tb.system_control.POR
18 system_control_tb.system_control.POR_ctr[3:0]
20 system_control_tb.clock_ready
21 system_control_tb.system_control.half_clk
22 system_control_tb.system_control.fin_ret_half
23 system_control_tb.system_control.fin_ret_aux
24 system_control_tb.system_control.gate_dsp_clk