3 * Copyright 2007 Free Software Foundation, Inc.
5 * This program is free software: you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation, either version 3 of the License, or
8 * (at your option) any later version.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program. If not, see <http://www.gnu.org/licenses/>.
20 // Wishbone National Semiconductor 16550A compatible UART
22 #ifndef INCLUDED_WB16550_H
23 #define INCLUDED_WB16550_H
28 volatile uint8_t data; // 0 r/w: r: rx fifo, w: tx fifo (if DLAB: LSB of divisor)
29 volatile uint8_t ier; // 1 r/w: Interrupt Enable Register (if DLAB: MSB of divisor)
30 volatile uint8_t iir_fcr; // 2 r/w: r: Interrupt ID Register,
31 // w: Fifo Control Register
32 volatile uint8_t lcr; // 3 r/w: Line Control Register
33 volatile uint8_t mcr; // 4 w: Modem Control Register
34 volatile uint8_t lsr; // 5 r: Line Status Register
35 volatile uint8_t msr; // 6 r: Modem Status Register
39 #define UART_IER_RDI 0x01 // Enable received data interrupt
40 #define UART_IER_THRI 0x02 // Enable transmitter holding reg empty int.
41 #define UART_IER_RLSI 0x04 // Enable receiver line status interrupt
42 #define UART_IER_MSI 0x08 // Enable modem status interrupt
44 #define UART_IIR_NO_INT 0x01 // No interrupts pending
45 #define UART_IIR_ID_MASK 0x06 // Mask for interrupt ID
46 #define UART_IIR_MSI 0x00 // Modem status interrupt
47 #define UART_IIR_THRI 0x02 // Tx holding register empty int
48 #define UART_IIR_RDI 0x04 // Rx data available int
49 #define UART_IIR_RLSI 0x06 // Receiver line status int
51 #define UART_FCR_ENABLE_FIFO 0x01 // ignore, always enabled
52 #define UART_FCR_CLEAR_RCVR 0x02 // Clear the RCVR FIFO
53 #define UART_FCR_CLEAR_XMIT 0x04 // Clear the XMIT FIFO
54 #define UART_FCR_TRIGGER_MASK 0xC0 // Mask for FIFO trigger range
55 #define UART_FCR_TRIGGER_1 0x00 // Rx fifo trigger level: 1 byte
56 #define UART_FCR_TRIGGER_4 0x40 // Rx fifo trigger level: 4 bytes
57 #define UART_FCR_TRIGGER_8 0x80 // Rx fifo trigger level: 8 bytes
58 #define UART_FCR_TRIGGER_14 0xC0 // Rx fifo trigger level: 14 bytes
60 #define UART_LCR_DLAB 0x80 // Divisor latch access bit
61 #define UART_LCR_SBC 0x40 // Set break control
62 #define UART_LCR_SPAR 0x20 // Stick parity
63 #define UART_LCR_EPAR 0x10 // Even parity select
64 #define UART_LCR_PARITY 0x08 // Parity Enable
65 #define UART_LCR_STOP 0x04 // Stop bits: 0=1 bit, 1=2 bits
66 #define UART_LCR_WLEN5 0x00 // Wordlength: 5 bits
67 #define UART_LCR_WLEN6 0x01 // Wordlength: 6 bits
68 #define UART_LCR_WLEN7 0x02 // Wordlength: 7 bits
69 #define UART_LCR_WLEN8 0x03 // Wordlength: 8 bits
71 #define UART_MCR_LOOP 0x10 // Enable loopback test mode
72 #define UART_MCR_OUT2n 0x08 // Out2 complement (loopback mode)
73 #define UART_MCR_OUT1n 0x04 // Out1 complement (loopback mode)
74 #define UART_MCR_RTSn 0x02 // RTS complement
75 #define UART_MCR_DTRn 0x01 // DTR complement
77 #define UART_LSR_TEMT 0x40 // Transmitter empty
78 #define UART_LSR_THRE 0x20 // Transmit-hold-register empty
79 #define UART_LSR_BI 0x10 // Break interrupt indicator
80 #define UART_LSR_FE 0x08 // Frame error indicator
81 #define UART_LSR_PE 0x04 // Parity error indicator
82 #define UART_LSR_OE 0x02 // Overrun error indicator
83 #define UART_LSR_DR 0x01 // Receiver data ready
84 #define UART_LSR_BRK_ERROR_BITS 0x1E // BI, FE, PE, OE bits
85 #define UART_LSR_ERROR 0x80 // At least 1 PE, FE or BI are in the fifo
87 #define UART_MSR_DCD 0x80 // Data Carrier Detect
88 #define UART_MSR_RI 0x40 // Ring Indicator
89 #define UART_MSR_DSR 0x20 // Data Set Ready
90 #define UART_MSR_CTS 0x10 // Clear to Send
91 #define UART_MSR_DDCD 0x08 // Delta DCD
92 #define UART_MSR_TERI 0x04 // Trailing edge ring indicator
93 #define UART_MSR_DDSR 0x02 // Delta DSR
94 #define UART_MSR_DCTS 0x01 // Delta CTS
95 #define UART_MSR_ANY_DELTA 0x0F // Any of the delta bits!
98 #endif // INCLUDED_WB16550_H