3 * Copyright 2007,2008,2009 Free Software Foundation, Inc.
5 * This program is free software: you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation, either version 3 of the License, or
8 * (at your option) any later version.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program. If not, see <http://www.gnu.org/licenses/>.
20 * 0000-7FFF 32K RAM space (16K on 1500, 24K on 2000, 32K on DSP)
21 * 8000-BFFF 16K Buffer Pool
22 * C000-FFFF 16K Peripherals
26 #ifndef INCLUDED_MEMORY_MAP_H
27 #define INCLUDED_MEMORY_MAP_H
32 #define MASTER_CLK_RATE 100000000 // 100 MHz
35 ////////////////////////////////////////////////////////////////
37 // Memory map for embedded wishbone bus
39 ////////////////////////////////////////////////////////////////
42 ////////////////////////////////////////////////////////////////
45 #define RAM_BASE 0x0000
47 ////////////////////////////////////////////////////////////////
48 // Buffer Pool RAM, Slave 1
50 // The buffers themselves are located in Slave 1, Buffer Pool RAM.
51 // The status registers are in Slave 5, Buffer Pool Status.
52 // The control register is in Slave 7, Settings Bus.
54 #define BUFFER_POOL_RAM_BASE 0x8000
57 #define BP_NLINES 0x0200 // number of 32-bit lines in a buffer
58 #define BP_LAST_LINE (BP_NLINES - 1) // last line in a buffer
60 #define buffer_pool_ram \
61 ((uint32_t *) BUFFER_POOL_RAM_BASE)
63 #define buffer_ram(n) (&buffer_pool_ram[(n) * BP_NLINES])
66 /////////////////////////////////////////////////////
67 // SPI Core, Slave 2. See core docs for more info
68 #define SPI_BASE 0xC000 // Base address (16-bit)
71 volatile uint32_t txrx0;
72 volatile uint32_t txrx1;
73 volatile uint32_t txrx2;
74 volatile uint32_t txrx3;
75 volatile uint32_t ctrl;
76 volatile uint32_t div;
80 #define spi_regs ((spi_regs_t *) SPI_BASE)
83 // Masks for controlling different peripherals
84 #define SPI_SS_AD9510 1
85 #define SPI_SS_AD9777 2
86 #define SPI_SS_RX_DAC 4
87 #define SPI_SS_RX_ADC 8
88 #define SPI_SS_RX_DB 16
89 #define SPI_SS_TX_DAC 32
90 #define SPI_SS_TX_ADC 64
91 #define SPI_SS_TX_DB 128
93 // Masks for different parts of CTRL reg
94 #define SPI_CTRL_ASS (1<<13)
95 #define SPI_CTRL_IE (1<<12)
96 #define SPI_CTRL_LSB (1<<11)
97 #define SPI_CTRL_TXNEG (1<<10)
98 #define SPI_CTRL_RXNEG (1<< 9)
99 #define SPI_CTRL_GO_BSY (1<< 8)
100 #define SPI_CTRL_CHAR_LEN_MASK 0x7F
102 ////////////////////////////////////////////////
104 // See Wishbone I2C-Master Core Specification.
106 #define I2C_BASE 0xC400
109 volatile uint32_t prescaler_lo; // r/w
110 volatile uint32_t prescaler_hi; // r/w
111 volatile uint32_t ctrl; // r/w
112 volatile uint32_t data; // wr = transmit reg; rd = receive reg
113 volatile uint32_t cmd_status; // wr = command reg; rd = status reg
116 #define i2c_regs ((i2c_regs_t *) I2C_BASE)
118 #define I2C_CTRL_EN (1 << 7) // core enable
119 #define I2C_CTRL_IE (1 << 6) // interrupt enable
122 // STA, STO, RD, WR, and IACK bits are cleared automatically
124 #define I2C_CMD_START (1 << 7) // generate (repeated) start condition
125 #define I2C_CMD_STOP (1 << 6) // generate stop condition
126 #define I2C_CMD_RD (1 << 5) // read from slave
127 #define I2C_CMD_WR (1 << 4) // write to slave
128 #define I2C_CMD_NACK (1 << 3) // when a rcvr, send ACK (ACK=0) or NACK (ACK=1)
129 #define I2C_CMD_RSVD_2 (1 << 2) // reserved
130 #define I2C_CMD_RSVD_1 (1 << 1) // reserved
131 #define I2C_CMD_IACK (1 << 0) // set to clear pending interrupt
133 #define I2C_ST_RXACK (1 << 7) // Received acknowledgement from slave (1 = NAK, 0 = ACK)
134 #define I2C_ST_BUSY (1 << 6) // 1 after START signal detected; 0 after STOP signal detected
135 #define I2C_ST_AL (1 << 5) // Arbitration lost. 1 when core lost arbitration
136 #define I2C_ST_RSVD_4 (1 << 4) // reserved
137 #define I2C_ST_RSVD_3 (1 << 3) // reserved
138 #define I2C_ST_RSVD_2 (1 << 2) // reserved
139 #define I2C_ST_TIP (1 << 1) // Transfer-in-progress
140 #define I2C_ST_IP (1 << 0) // Interrupt pending
143 ////////////////////////////////////////////////
146 // These go to the daughterboard i/o pins
148 #define GPIO_BASE 0xC800
151 volatile uint32_t io; // tx data in high 16, rx in low 16
152 volatile uint32_t ddr; // 32 bits, 1 means output. tx in high 16, rx in low 16
153 volatile uint32_t tx_sel; // 16 2-bit fields select which source goes to TX DB
154 volatile uint32_t rx_sel; // 16 2-bit fields select which source goes to RX DB
157 // each 2-bit sel field is layed out this way
158 #define GPIO_SEL_SW 0 // if pin is an output, set by software in the io reg
159 #define GPIO_SEL_ATR 1 // if pin is an output, set by ATR logic
160 #define GPIO_SEL_DEBUG_0 2 // if pin is an output, debug lines from FPGA fabric
161 #define GPIO_SEL_DEBUG_1 3 // if pin is an output, debug lines from FPGA fabric
163 #define gpio_base ((gpio_regs_t *) GPIO_BASE)
165 ///////////////////////////////////////////////////
166 // Buffer Pool Status, Slave 5
168 // The buffers themselves are located in Slave 1, Buffer Pool RAM.
169 // The status registers are in Slave 5, Buffer Pool Status.
170 // The control register is in Slave 7, Settings Bus.
172 #define BUFFER_POOL_STATUS_BASE 0xCC00
175 volatile uint32_t last_line[NBUFFERS]; // last line xfer'd in buffer
176 volatile uint32_t status; // error and done flags
177 volatile uint32_t hw_config; // see below
178 } buffer_pool_status_t;
180 #define buffer_pool_status ((buffer_pool_status_t *) BUFFER_POOL_STATUS_BASE)
183 * Buffer n's xfer is done.
184 * Clear this bit by issuing bp_clear_buf(n)
186 #define BPS_DONE(n) (0x00000001 << (n))
187 #define BPS_DONE_0 BPS_DONE(0)
188 #define BPS_DONE_1 BPS_DONE(1)
189 #define BPS_DONE_2 BPS_DONE(2)
190 #define BPS_DONE_3 BPS_DONE(3)
191 #define BPS_DONE_4 BPS_DONE(4)
192 #define BPS_DONE_5 BPS_DONE(5)
193 #define BPS_DONE_6 BPS_DONE(6)
194 #define BPS_DONE_7 BPS_DONE(7)
197 * Buffer n's xfer had an error.
198 * Clear this bit by issuing bp_clear_buf(n)
200 #define BPS_ERROR(n) (0x00000100 << (n))
201 #define BPS_ERROR_0 BPS_ERROR(0)
202 #define BPS_ERROR_1 BPS_ERROR(1)
203 #define BPS_ERROR_2 BPS_ERROR(2)
204 #define BPS_ERROR_3 BPS_ERROR(3)
205 #define BPS_ERROR_4 BPS_ERROR(4)
206 #define BPS_ERROR_5 BPS_ERROR(5)
207 #define BPS_ERROR_6 BPS_ERROR(6)
208 #define BPS_ERROR_7 BPS_ERROR(7)
211 * Buffer n is idle. A buffer is idle if it's not
212 * DONE, ERROR, or processing a transaction. If it's
213 * IDLE, it's safe to start a new transaction.
215 * Clear this bit by starting a xfer with
216 * bp_send_from_buf or bp_receive_to_buf.
218 #define BPS_IDLE(n) (0x00010000 << (n))
219 #define BPS_IDLE_0 BPS_IDLE(0)
220 #define BPS_IDLE_1 BPS_IDLE(1)
221 #define BPS_IDLE_2 BPS_IDLE(2)
222 #define BPS_IDLE_3 BPS_IDLE(3)
223 #define BPS_IDLE_4 BPS_IDLE(4)
224 #define BPS_IDLE_5 BPS_IDLE(5)
225 #define BPS_IDLE_6 BPS_IDLE(6)
226 #define BPS_IDLE_7 BPS_IDLE(7)
229 * Buffer n has a "slow path" packet in it.
230 * This bit is orthogonal to the bits above and indicates that
231 * the FPGA ethernet rx protocol engine has identified this packet
232 * as one requiring firmware intervention.
234 #define BPS_SLOWPATH(n) (0x01000000 << (n))
235 #define BPS_SLOWPATH_0 BPS_SLOWPATH(0)
236 #define BPS_SLOWPATH_1 BPS_SLOWPATH(1)
237 #define BPS_SLOWPATH_2 BPS_SLOWPATH(2)
238 #define BPS_SLOWPATH_3 BPS_SLOWPATH(3)
239 #define BPS_SLOWPATH_4 BPS_SLOWPATH(4)
240 #define BPS_SLOWPATH_5 BPS_SLOWPATH(5)
241 #define BPS_SLOWPATH_6 BPS_SLOWPATH(6)
242 #define BPS_SLOWPATH_7 BPS_SLOWPATH(7)
245 #define BPS_DONE_ALL 0x000000ff // mask of all dones
246 #define BPS_ERROR_ALL 0x0000ff00 // mask of all errors
247 #define BPS_IDLE_ALL 0x00ff0000 // mask of all idles
248 #define BPS_SLOWPATH_ALL 0xff000000 // mask of all slowpaths
250 // The hw_config register
252 #define HWC_SIMULATION 0x80000000
253 #define HWC_WB_CLK_DIV_MASK 0x0000000f
256 * \brief return non-zero if we're running under the simulator
259 hwconfig_simulation_p(void)
261 return buffer_pool_status->hw_config & HWC_SIMULATION;
265 * \brief Return Wishbone Clock divisor.
266 * The processor runs at the Wishbone Clock rate which is MASTER_CLK_RATE / divisor.
269 hwconfig_wishbone_divisor(void)
271 return buffer_pool_status->hw_config & HWC_WB_CLK_DIV_MASK;
274 ///////////////////////////////////////////////////
275 // Ethernet Core, Slave 6
277 #define ETH_BASE 0xD000
279 #include "eth_mac_regs.h"
281 #define eth_mac ((eth_mac_regs_t *) ETH_BASE)
283 ////////////////////////////////////////////////////
284 // Settings Bus, Slave #7, Not Byte Addressable!
286 // Output-only from processor point-of-view.
287 // 1KB of address space (== 256 32-bit write-only regs)
290 #define MISC_OUTPUT_BASE 0xD400
291 #define TX_PROTOCOL_ENGINE_BASE 0xD480
292 #define RX_PROTOCOL_ENGINE_BASE 0xD4C0
293 #define BUFFER_POOL_CTRL_BASE 0xD500
294 #define DSP_TX_BASE 0xD600
295 #define DSP_RX_BASE 0xD680
297 #define LAST_SETTING_REG 0xD7FC // last valid setting register
299 // --- buffer pool control regs ---
302 volatile uint32_t ctrl;
303 } buffer_pool_ctrl_t;
307 #define PORT_SERDES 0 // serial/deserializer
308 #define PORT_DSP 1 // DSP tx or rx pipeline
309 #define PORT_ETH 2 // ethernet tx or rx
310 #define PORT_RAM 3 // RAM tx or rx
312 // the buffer pool ctrl register fields
314 #define BPC_BUFFER(n) (((n) & 0xf) << 28)
315 #define BPC_BUFFER_MASK BPC_BUFFER(~0)
316 #define BPC_BUFFER_0 BPC_BUFFER(0)
317 #define BPC_BUFFER_1 BPC_BUFFER(1)
318 #define BPC_BUFFER_2 BPC_BUFFER(2)
319 #define BPC_BUFFER_3 BPC_BUFFER(3)
320 #define BPC_BUFFER_4 BPC_BUFFER(4)
321 #define BPC_BUFFER_5 BPC_BUFFER(5)
322 #define BPC_BUFFER_6 BPC_BUFFER(6)
323 #define BPC_BUFFER_7 BPC_BUFFER(7)
324 #define BPC_BUFFER_NIL BPC_BUFFER(0x8) // disable
326 #define BPC_PORT(n) (((n) & 0x7) << 25)
327 #define BPC_PORT_MASK BPC_PORT(~0)
328 #define BPC_PORT_SERDES BPC_PORT(PORT_SERDES)
329 #define BPC_PORT_DSP BPC_PORT(PORT_DSP)
330 #define BPC_PORT_ETH BPC_PORT(PORT_ETH)
331 #define BPC_PORT_RAM BPC_PORT(PORT_RAM)
332 #define BPC_PORT_NIL BPC_PORT(0x4) // disable
334 #define BPC_CLR (1 << 24) // mutually excl commands
335 #define BPC_READ (1 << 23)
336 #define BPC_WRITE (1 << 22)
338 #define BPC_STEP(step) (((step) & 0xf) << 18)
339 #define BPC_STEP_MASK BPC_STEP(~0)
340 #define BPC_LAST_LINE(line) (((line) & 0x1ff) << 9)
341 #define BPC_LAST_LINE_MASK BPC_LAST_LINE(~0)
342 #define BPC_FIRST_LINE(line) (((line) & 0x1ff) << 0)
343 #define BPC_FIRST_LINE_MASK BPC_FIRST_LINE(~0)
345 #define buffer_pool_ctrl ((buffer_pool_ctrl_t *) BUFFER_POOL_CTRL_BASE)
347 // --- misc outputs ---
350 volatile uint32_t clk_ctrl;
351 volatile uint32_t serdes_ctrl;
352 volatile uint32_t adc_ctrl;
353 volatile uint32_t leds;
354 volatile uint32_t phy_ctrl; // LSB is reset line to eth phy
355 volatile uint32_t debug_mux_ctrl;
356 volatile uint32_t ram_page; // FIXME should go somewhere else...
357 volatile uint32_t flush_icache; // Flush the icache
358 volatile uint32_t led_src; // HW or SW control for LEDs
361 #define SERDES_ENABLE 8
362 #define SERDES_PRBSEN 4
363 #define SERDES_LOOPEN 2
364 #define SERDES_RXEN 1
366 #define ADC_CTRL_ON 0x0F
367 #define ADC_CTRL_OFF 0x00
369 // crazy order that matches the labels on the case
371 #define LED_A (1 << 4)
372 #define LED_B (1 << 1)
373 #define LED_C (1 << 3)
374 #define LED_D (1 << 0)
375 #define LED_E (1 << 2)
376 // LED_F // controlled by CPLD
377 #define LED_RJ45 (1 << 5)
379 #define output_regs ((output_regs_t *) MISC_OUTPUT_BASE)
381 // --- dsp tx regs ---
383 #define MIN_CIC_INTERP 1
384 #define MAX_CIC_INTERP 128
387 volatile int32_t freq;
388 volatile uint32_t scale_iq; // {scale_i,scale_q}
389 volatile uint32_t interp_rate;
390 volatile uint32_t clear_state; // clears out state machine, fifos,
391 // NOT freq, scale, interp
393 * \brief output mux configuration.
397 * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
398 * +-------------------------------+-------+-------+-------+-------+
400 * +-------------------------------+-------+-------+-------+-------+
402 * There are N DUCs (1 now) with complex inputs and outputs.
403 * There are two DACs.
405 * Each 4-bit DACx field specifies the source for the DAC
406 * Each subfield is coded like this:
413 * N specifies which DUC output is connected to this DAC.
415 * N which interp output
416 * --- -------------------
423 * The default value is 0x10
426 volatile uint32_t tx_mux;
430 #define dsp_tx_regs ((dsp_tx_regs_t *) DSP_TX_BASE)
432 // --- dsp rx regs ---
436 #define MIN_CIC_DECIM 1
437 #define MAX_CIC_DECIM 128
440 volatile int32_t freq;
441 volatile uint32_t scale_iq; // {scale_i,scale_q}
442 volatile uint32_t decim_rate;
443 volatile uint32_t rx_time; // when to begin reception
444 volatile uint32_t rx_command; // {now, chain, num_lines(21), lines_per_frame(9)
445 volatile uint32_t clear_state; // clears out state machine, fifos,
446 // cmd queue, NOT freq, scale, decim
447 volatile uint32_t dcoffset_i; // Bit 31 high sets fixed offset mode, using lower 14 bits,
448 // otherwise it is automatic
449 volatile uint32_t dcoffset_q; // Bit 31 high sets fixed offset mode, using lower 14 bits
452 * \brief input mux configuration.
454 * This determines which ADC (or constant zero) is connected to
455 * each DDC input. There are N DDCs (1 now). Each has two inputs.
461 * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
462 * +-------+-------+-------+-------+-------+-------+-------+-------+
464 * +-------+-------+-------+-------+-------+-------+-------+-------+
466 * Each 2-bit I field is either 00 (A/D A), 01 (A/D B) or 1X (const zero)
467 * Each 2-bit Q field is either 00 (A/D A), 01 (A/D B) or 1X (const zero)
469 * The default value is 0x4
472 volatile uint32_t rx_mux; // called adc_mux in dsp_core_rx.v
475 * \brief Streaming GPIO configuration
477 * This determines whether the LSBs of I and Q samples come from the DSP
478 * pipeline or from the io_rx GPIO pins. To stream GPIO, one must first
479 * set the GPIO data direction register to have io_rx[15] and/or io_rx[14]
480 * configured as inputs. The GPIO pins will be sampled at the time the
481 * remainder of the DSP sample is strobed into the RX sample FIFO. There
482 * will be a decimation-dependent fixed time offset between the GPIO
483 * sample stream and the associated RF samples.
486 * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
487 * +-------+-------+-------+-------+-------+-------+-------+-------+
489 * +-------+-------+-------+-------+-------+-------+-------+-------+
491 * I 0=LSB comes from DSP pipeline (default)
492 * 1=LSB comes from io_rx[15]
494 * Q 0=LSB comes from DSP pipeline (default)
495 * 1=LSB comes from io_rx[14]
497 volatile uint32_t gpio_stream_enable;
501 #define dsp_rx_regs ((dsp_rx_regs_t *) DSP_RX_BASE)
503 #define MK_RX_CMD(num_lines, lines_per_frame, now, chain) \
504 (((num_lines) << 9) | ((lines_per_frame) & 0x1ff) \
505 | (((now) & 0x1) << 31) | (((chain) & 0x1) << 30))
508 * --- ethernet tx protocol engine regs (write only) ---
510 * These registers control the transmit portion of the ethernet
511 * protocol engine (out of USRP2). The protocol engine handles fifo
512 * status and sequence number insertion in outgoing packets, and
513 * automagically generates status packets when required to inform the
514 * host of changes in fifo availability.
516 * All outgoing packets have their fifo_status field set to the number
517 * of 32-bit lines of fifo available in the ethernet Rx fifo (see
518 * usrp2_eth_packet.h). Seqno's are set if FIXME, else 0.
520 * FIXME clean this up once we know how it's supposed to behave.
524 volatile uint32_t flags; // not yet fully defined (channel?)
525 volatile uint32_t mac_dst0123; // 4 bytes of destination mac addr
526 volatile uint32_t mac_dst45src01; // 2 bytes of dest mac addr; 2 bytes of src mac addr
527 volatile uint32_t mac_src2345; // 4 bytes of destination mac addr
528 volatile uint32_t seqno; // Write to init seqno. It autoincs on match
529 } tx_proto_engine_regs_t;
531 #define tx_proto_engine ((tx_proto_engine_regs_t *) TX_PROTOCOL_ENGINE_BASE)
534 * --- ethernet rx protocol engine regs (write only) ---
536 * These registers control the receive portion of the ethernet
537 * protocol engine (into USRP2). The protocol engine offloads common
538 * packet inspection operations so that firmware has less to do on
539 * "fast path" packets.
541 * The registers define conditions which must be matched for a packet
542 * to be considered a "fast path" packet. If a received packet
543 * matches the src and dst mac address, ethertype, flags field, and
544 * expected seqno number it is considered a "fast path" packet, and
545 * the expected seqno is updated. If the packet fails to satisfy any
546 * of the above conditions it's a "slow path" packet, and the
547 * corresponding SLOWPATH flag will be set buffer_status register.
551 volatile uint32_t flags; // not yet fully defined (channel?)
552 volatile uint32_t mac_dst0123; // 4 bytes of destination mac addr
553 volatile uint32_t mac_dst45src01; // 2 bytes of dest mac addr; 2 bytes of src mac addr
554 volatile uint32_t mac_src2345; // 4 bytes of destination mac addr
555 volatile uint32_t ethertype_pad; // ethertype in high 16-bits
556 } rx_proto_engine_regs_t;
558 #define rx_proto_engine ((rx_proto_engine_regs_t *) RX_PROTOCOL_ENGINE_BASE)
562 ///////////////////////////////////////////////////
563 // Simple Programmable Interrupt Controller, Slave 8
565 #define PIC_BASE 0xD800
567 // Interrupt request lines
568 // Bit numbers (LSB == 0) that correpond to interrupts into PIC
570 #define IRQ_BUFFER 0 // buffer manager
574 #define IRQ_PHY 4 // ethernet PHY
575 #define IRQ_UNDERRUN 5
576 #define IRQ_OVERRUN 6
577 #define IRQ_PPS 7 // pulse per second
578 #define IRQ_UART_RX 8
579 #define IRQ_UART_TX 9
580 #define IRQ_SERDES 10
581 #define IRQ_CLKSTATUS 11
583 #define IRQ_TO_MASK(x) (1 << (x))
585 #define PIC_BUFFER_INT IRQ_TO_MASK(IRQ_BUFFER)
586 #define PIC_TIMER_INT IRQ_TO_MASK(IRQ_TIMER)
587 #define PIC_SPI_INT IRQ_TO_MASK(IRQ_SPI)
588 #define PIC_I2C_INT IRQ_TO_MASK(IRQ_I2C)
589 #define PIC_PHY_INT IRQ_TO_MASK(IRQ_PHY)
590 #define PIC_UNDERRUN_INT IRQ_TO_MASK(IRQ_UNDERRUN)
591 #define PIC_OVERRUN_INT IRQ_TO_MASK(IRQ_OVERRUN)
592 #define PIC_PPS_INT IRQ_TO_MASK(IRQ_PPS)
593 #define PIC_UART_RX_INT IRQ_TO_MASK(IRQ_UART_RX)
594 #define PIC_UART_TX_INT IRQ_TO_MASK(IRQ_UART_TX)
595 #define PIC_SERDES IRQ_TO_MASK(IRQ_SERDES)
596 #define PIC_CLKSTATUS IRQ_TO_MASK(IRQ_CLKSTATUS)
599 volatile uint32_t edge_enable; // mask: 1 -> edge triggered, 0 -> level
600 volatile uint32_t polarity; // mask: 1 -> rising edge
601 volatile uint32_t mask; // mask: 1 -> disabled
602 volatile uint32_t pending; // mask: 1 -> pending; write 1's to clear pending ints
605 #define pic_regs ((pic_regs_t *) PIC_BASE)
607 ///////////////////////////////////////////////////
610 #define TIMER_BASE 0xDC00
613 volatile uint32_t time; // R: current, W: set time to interrupt
616 #define timer_regs ((timer_regs_t *) TIMER_BASE)
618 ///////////////////////////////////////////////////
621 #define UART_BASE 0xE000
624 // All elements are 8 bits except for clkdiv (16), but we use uint32 to make
625 // the hardware for decoding easier
626 volatile uint32_t clkdiv; // Set to 50e6 divided by baud rate (no x16 factor)
627 volatile uint32_t txlevel; // Number of spaces in the FIFO for writes
628 volatile uint32_t rxlevel; // Number of available elements in the FIFO for reads
629 volatile uint32_t txchar; // Write characters to be sent here
630 volatile uint32_t rxchar; // Read received characters here
633 #define uart_regs ((uart_regs_t *) UART_BASE)
635 ///////////////////////////////////////////////////
636 // ATR Controller, Slave 11
638 #define ATR_BASE 0xE400
641 volatile uint32_t v[16];
644 #define ATR_IDLE 0x0 // indicies into v
649 #define atr_regs ((atr_regs_t *) ATR_BASE)
651 ///////////////////////////////////////////////////
652 // Time Sync Controller, Slave 12
653 #define TIMESYNC_BASE 0xE800
657 * \brief Time sync configuration.
662 * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
663 * +-----------------------------------------------------+-+-+-+-+-+
665 * +-----------------------------------------------------+-+-+-+-+-+
667 * S - Tick source (0 = free run, 1 = pps, default=0)
668 * I - Tick interrupt enable (not implemented)
669 * X - Use external sync source (default=1)
670 * G - PPS edge selection (0=negedge, 1=posedge, default=0)
671 * T - Trigger sync every pps edge (default=0)
675 volatile uint32_t tick_control;
676 volatile uint32_t tick_interval;
677 volatile uint32_t delta_time;
678 volatile uint32_t sync_on_next_pps;
681 #define timesync_regs ((timesync_regs_t *) TIMESYNC_BASE)
683 #define TSC_SOURCE_PPS (1 << 0)
684 //#define TSC_SOURCE_FREE_RUN (0 << 0)
685 #define TSC_IENABLE (1 << 1)
686 #define TSC_EXTSYNC (1 << 2)
687 #define TSC_PPSEDGE_POS (1 << 3)
688 //#define TSC_PPSEDGE_NEG (0 << 3)
689 #define TSC_TRIGGER_EVERYPPS (1 << 4)
690 //#define TSC_TRIGGER_ONCE (0 << 4)
692 ///////////////////////////////////////////////////
693 // SD Card SPI interface, Slave 13
694 // All regs are 8 bits wide, but are accessed as if they are 32 bits
696 #define SDSPI_BASE 0xEC00
699 volatile uint32_t status; // Write a 1 or 0 for controlling CS
700 volatile uint32_t clkdiv;
701 volatile uint32_t send_dat;
702 volatile uint32_t receive_dat;
705 #define sdspi_regs ((sdspi_regs_t *) SDSPI_BASE)
707 ///////////////////////////////////////////////////
708 // External RAM interface, Slave 14
709 // Pages are 1K. Page is 10 bits, set by a control register
710 // output_regs->ram_page
712 #define EXTRAM_BASE 0xF000
713 #define extram ((volatile uint32_t *) EXTRAM_BASE)
716 ///////////////////////////////////////////////////