2 * Copyright 2008,2009 Free Software Foundation, Inc.
4 * This program is free software: you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation, either version 3 of the License, or
7 * (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
14 * You should have received a copy of the GNU General Public License
15 * along with this program. If not, see <http://www.gnu.org/licenses/>.
19 #include <memory_map.h>
28 bool rfx_init_rx(struct db_base *db);
29 bool rfx_init_tx(struct db_base *db);
30 bool rfx_set_freq(struct db_base *db, u2_fxpt_freq_t freq, u2_fxpt_freq_t *dc);
31 bool rfx_set_gain_rx(struct db_base *db, u2_fxpt_gain_t gain);
32 bool rfx_set_gain_tx(struct db_base *db, u2_fxpt_gain_t gain);
33 bool rfx_set_tx_enable(struct db_base *, bool on);
35 // Control Latch Defines
36 #define P 0 // Prescalar value for setting in regs, must match the next line...
37 #define PRESCALER 8 // Presacalar value for computations
38 #define PD 0 // Power down, 0 = normal operation
39 #define PL 0 // PLL power output
40 #define MTLD 1 // Mute till lock detect
41 #define CPGAIN 0 // Charge pump gain, use setting 1, also in N-reg
42 #define CP3S 0 // Charge pump tri-state, 0 = normal operation
43 #define PDP 1 // Phase detector polarity
44 #define MUXOUT 1 // Digital lock detect, active high
45 #define CR 0 // normal operation
46 #define PC 1 // core power
49 #define DIVSEL 0 // N Counter always operates on full rate
60 #define phdet_freq (U2_DOUBLE_TO_FXPT_FREQ(100e6/R_DIV))
63 #define POWER_UP (1 << 7) // Low enables power supply
64 #define ANT_SW (1 << 6) // On TX DB, 0 = TX, 1 = RX, on RX DB 0 = main ant, 1 = RX2
65 #define MIX_EN (1 << 5) // Enable appropriate mixer
66 #define LOCKDET_MASK (1 << 2) // Input pin
68 struct db_rfx_common {
79 struct db_rfx_common common;
83 struct db_rfx_400_rx {
85 struct db_rfx_common common;
88 struct db_rfx_400_tx {
90 struct db_rfx_common common;
93 struct db_rfx_900_rx {
95 struct db_rfx_common common;
98 struct db_rfx_900_tx {
100 struct db_rfx_common common;
103 struct db_rfx_1200_rx {
105 struct db_rfx_common common;
108 struct db_rfx_1200_tx {
110 struct db_rfx_common common;
113 struct db_rfx_1800_rx {
115 struct db_rfx_common common;
118 struct db_rfx_1800_tx {
120 struct db_rfx_common common;
123 struct db_rfx_2400_rx {
125 struct db_rfx_common common;
128 struct db_rfx_2400_tx {
130 struct db_rfx_common common;
135 * The class instances
137 struct db_rfx_400_rx db_rfx_400_rx = {
140 .base.output_enables = 0x00E0,
141 .base.used_pins = 0x00FF,
142 .base.freq_min = U2_DOUBLE_TO_FXPT_FREQ(400e6),
143 .base.freq_max = U2_DOUBLE_TO_FXPT_FREQ(500e6),
144 .base.gain_min = U2_DOUBLE_TO_FXPT_GAIN(0),
145 .base.gain_max = U2_DOUBLE_TO_FXPT_GAIN(45),
146 .base.gain_step_size = U2_DOUBLE_TO_FXPT_GAIN(0.022),
147 .base.is_quadrature = true,
148 .base.i_and_q_swapped = true,
149 .base.spectrum_inverted = false,
150 .base.default_lo_offset = U2_DOUBLE_TO_FXPT_FREQ(0),
151 .base.init = rfx_init_rx,
152 .base.set_freq = rfx_set_freq,
153 .base.set_gain = rfx_set_gain_rx,
154 .base.set_tx_enable = 0,
155 .base.atr_mask = 0x00E0,
156 .base.atr_txval = POWER_UP,
157 .base.atr_rxval = POWER_UP|MIX_EN,
158 // .base.atr_tx_delay =
159 // .base.atr_rx_delay =
160 .base.set_antenna = 0,
164 .common.spi_mask = SPI_SS_RX_DB,
165 .common.freq_mult = 2
169 struct db_rfx_400_tx db_rfx_400_tx = {
172 .base.output_enables = 0x00E0,
173 .base.used_pins = 0x00FF,
174 .base.freq_min = U2_DOUBLE_TO_FXPT_FREQ(400e6),
175 .base.freq_max = U2_DOUBLE_TO_FXPT_FREQ(500e6),
176 //.base.gain_min = U2_DOUBLE_TO_FXPT_GAIN(xxx),
177 //.base.gain_max = U2_DOUBLE_TO_FXPT_GAIN(xxx),
178 //.base.gain_step_size = U2_DOUBLE_TO_FXPT_GAIN(xxx),
179 .base.is_quadrature = true,
180 .base.i_and_q_swapped = false,
181 .base.spectrum_inverted = false,
182 .base.default_lo_offset = U2_DOUBLE_TO_FXPT_FREQ(12.5e6),
183 .base.init = rfx_init_tx,
184 .base.set_freq = rfx_set_freq,
185 .base.set_gain = rfx_set_gain_tx,
186 .base.set_tx_enable = rfx_set_tx_enable,
187 .base.atr_mask = 0x00E0,
188 .base.atr_txval = POWER_UP|MIX_EN,
189 .base.atr_rxval = POWER_UP|ANT_SW,
190 // .base.atr_tx_delay =
191 // .base.atr_rx_delay =
192 .base.set_antenna = 0,
196 .common.spi_mask = SPI_SS_TX_DB,
197 .common.freq_mult = 2
200 struct db_rfx_900_rx db_rfx_900_rx = {
203 .base.output_enables = 0x00E0,
204 .base.used_pins = 0x00FF,
205 .base.freq_min = U2_DOUBLE_TO_FXPT_FREQ(750e6),
206 .base.freq_max = U2_DOUBLE_TO_FXPT_FREQ(1050e6),
207 .base.gain_min = U2_DOUBLE_TO_FXPT_GAIN(0),
208 .base.gain_max = U2_DOUBLE_TO_FXPT_GAIN(70),
209 .base.gain_step_size = U2_DOUBLE_TO_FXPT_GAIN(0.034),
210 .base.is_quadrature = true,
211 .base.i_and_q_swapped = true,
212 .base.spectrum_inverted = false,
213 .base.default_lo_offset = U2_DOUBLE_TO_FXPT_FREQ(0),
214 .base.init = rfx_init_rx,
215 .base.set_freq = rfx_set_freq,
216 .base.set_gain = rfx_set_gain_rx,
217 .base.set_tx_enable = 0,
218 .base.atr_mask = 0x00E0,
220 .base.atr_rxval = MIX_EN,
221 // .base.atr_tx_delay =
222 // .base.atr_rx_delay =
223 .base.set_antenna = 0,
227 .common.spi_mask = SPI_SS_RX_DB,
228 .common.freq_mult = 2
232 struct db_rfx_900_tx db_rfx_900_tx = {
235 .base.output_enables = 0x00E0,
236 .base.used_pins = 0x00FF,
237 .base.freq_min = U2_DOUBLE_TO_FXPT_FREQ(750e6),
238 .base.freq_max = U2_DOUBLE_TO_FXPT_FREQ(1050e6),
239 //.base.gain_min = U2_DOUBLE_TO_FXPT_GAIN(xxx),
240 //.base.gain_max = U2_DOUBLE_TO_FXPT_GAIN(xxx),
241 //.base.gain_step_size = U2_DOUBLE_TO_FXPT_GAIN(xxx),
242 .base.is_quadrature = true,
243 .base.i_and_q_swapped = false,
244 .base.spectrum_inverted = false,
245 .base.default_lo_offset = U2_DOUBLE_TO_FXPT_FREQ(12.5e6),
246 .base.init = rfx_init_tx,
247 .base.set_freq = rfx_set_freq,
248 .base.set_gain = rfx_set_gain_tx,
249 .base.set_tx_enable = rfx_set_tx_enable,
250 .base.atr_mask = 0x00E0,
251 .base.atr_txval = MIX_EN,
252 .base.atr_rxval = ANT_SW,
253 // .base.atr_tx_delay =
254 // .base.atr_rx_delay =
255 .base.set_antenna = 0,
259 .common.spi_mask = SPI_SS_TX_DB,
260 .common.freq_mult = 2
263 struct db_rfx_1200_rx db_rfx_1200_rx = {
266 .base.output_enables = 0x00E0,
267 .base.used_pins = 0x00FF,
268 .base.freq_min = U2_DOUBLE_TO_FXPT_FREQ(1150e6),
269 .base.freq_max = U2_DOUBLE_TO_FXPT_FREQ(1450e6),
270 .base.gain_min = U2_DOUBLE_TO_FXPT_GAIN(0),
271 .base.gain_max = U2_DOUBLE_TO_FXPT_GAIN(70),
272 .base.gain_step_size = U2_DOUBLE_TO_FXPT_GAIN(0.034),
273 .base.is_quadrature = true,
274 .base.i_and_q_swapped = true,
275 .base.spectrum_inverted = false,
276 .base.default_lo_offset = U2_DOUBLE_TO_FXPT_FREQ(0),
277 .base.init = rfx_init_rx,
278 .base.set_freq = rfx_set_freq,
279 .base.set_gain = rfx_set_gain_rx,
280 .base.set_tx_enable = 0,
281 .base.atr_mask = 0x00E0,
283 .base.atr_rxval = MIX_EN,
284 // .base.atr_tx_delay =
285 // .base.atr_rx_delay =
286 .base.set_antenna = 0,
290 .common.spi_mask = SPI_SS_RX_DB,
291 .common.freq_mult = 2
295 struct db_rfx_1200_tx db_rfx_1200_tx = {
298 .base.output_enables = 0x00E0,
299 .base.used_pins = 0x00FF,
300 .base.freq_min = U2_DOUBLE_TO_FXPT_FREQ(1150e6),
301 .base.freq_max = U2_DOUBLE_TO_FXPT_FREQ(1450e6),
302 //.base.gain_min = U2_DOUBLE_TO_FXPT_GAIN(xxx),
303 //.base.gain_max = U2_DOUBLE_TO_FXPT_GAIN(xxx),
304 //.base.gain_step_size = U2_DOUBLE_TO_FXPT_GAIN(xxx),
305 .base.is_quadrature = true,
306 .base.i_and_q_swapped = false,
307 .base.spectrum_inverted = false,
308 .base.default_lo_offset = U2_DOUBLE_TO_FXPT_FREQ(12.5e6),
309 .base.init = rfx_init_tx,
310 .base.set_freq = rfx_set_freq,
311 .base.set_gain = rfx_set_gain_tx,
312 .base.set_tx_enable = rfx_set_tx_enable,
313 .base.atr_mask = 0x00E0,
314 .base.atr_txval = MIX_EN,
315 .base.atr_rxval = ANT_SW,
316 // .base.atr_tx_delay =
317 // .base.atr_rx_delay =
318 .base.set_antenna = 0,
322 .common.spi_mask = SPI_SS_TX_DB,
323 .common.freq_mult = 2
326 struct db_rfx_1800_rx db_rfx_1800_rx = {
329 .base.output_enables = 0x00E0,
330 .base.used_pins = 0x00FF,
331 .base.freq_min = U2_DOUBLE_TO_FXPT_FREQ(1500e6),
332 .base.freq_max = U2_DOUBLE_TO_FXPT_FREQ(2100e6),
333 .base.gain_min = U2_DOUBLE_TO_FXPT_GAIN(0),
334 .base.gain_max = U2_DOUBLE_TO_FXPT_GAIN(70),
335 .base.gain_step_size = U2_DOUBLE_TO_FXPT_GAIN(0.034),
336 .base.is_quadrature = true,
337 .base.i_and_q_swapped = true,
338 .base.spectrum_inverted = false,
339 .base.default_lo_offset = U2_DOUBLE_TO_FXPT_FREQ(0),
340 .base.init = rfx_init_rx,
341 .base.set_freq = rfx_set_freq,
342 .base.set_gain = rfx_set_gain_rx,
343 .base.set_tx_enable = 0,
344 .base.atr_mask = 0x00E0,
346 .base.atr_rxval = MIX_EN,
347 // .base.atr_tx_delay =
348 // .base.atr_rx_delay =
349 .base.set_antenna = 0,
353 .common.spi_mask = SPI_SS_RX_DB,
354 .common.freq_mult = 1
358 struct db_rfx_1800_tx db_rfx_1800_tx = {
361 .base.output_enables = 0x00E0,
362 .base.used_pins = 0x00FF,
363 .base.freq_min = U2_DOUBLE_TO_FXPT_FREQ(1500e6),
364 .base.freq_max = U2_DOUBLE_TO_FXPT_FREQ(2100e6),
365 //.base.gain_min = U2_DOUBLE_TO_FXPT_GAIN(xxx),
366 //.base.gain_max = U2_DOUBLE_TO_FXPT_GAIN(xxx),
367 //.base.gain_step_size = U2_DOUBLE_TO_FXPT_GAIN(xxx),
368 .base.is_quadrature = true,
369 .base.i_and_q_swapped = false,
370 .base.spectrum_inverted = false,
371 .base.default_lo_offset = U2_DOUBLE_TO_FXPT_FREQ(12.5e6),
372 .base.init = rfx_init_tx,
373 .base.set_freq = rfx_set_freq,
374 .base.set_gain = rfx_set_gain_tx,
375 .base.set_tx_enable = rfx_set_tx_enable,
376 .base.atr_mask = 0x00E0,
377 .base.atr_txval = MIX_EN,
378 .base.atr_rxval = ANT_SW,
379 // .base.atr_tx_delay =
380 // .base.atr_rx_delay =
381 .base.set_antenna = 0,
385 .common.spi_mask = SPI_SS_TX_DB,
386 .common.freq_mult = 1
390 struct db_rfx_2400_rx db_rfx_2400_rx = {
393 .base.output_enables = 0x00E0,
394 .base.used_pins = 0x00FF,
395 .base.freq_min = U2_DOUBLE_TO_FXPT_FREQ(2300e6),
396 .base.freq_max = U2_DOUBLE_TO_FXPT_FREQ(2900e6),
397 .base.gain_min = U2_DOUBLE_TO_FXPT_GAIN(0),
398 .base.gain_max = U2_DOUBLE_TO_FXPT_GAIN(70),
399 .base.gain_step_size = U2_DOUBLE_TO_FXPT_GAIN(0.034),
400 .base.is_quadrature = true,
401 .base.i_and_q_swapped = true,
402 .base.spectrum_inverted = false,
403 .base.default_lo_offset = U2_DOUBLE_TO_FXPT_FREQ(0),
404 .base.init = rfx_init_rx,
405 .base.set_freq = rfx_set_freq,
406 .base.set_gain = rfx_set_gain_rx,
407 .base.set_tx_enable = 0,
408 .base.atr_mask = 0x00E0,
410 .base.atr_rxval = MIX_EN,
411 // .base.atr_tx_delay =
412 // .base.atr_rx_delay =
413 .base.set_antenna = 0,
417 .common.spi_mask = SPI_SS_RX_DB,
418 .common.freq_mult = 1
422 struct db_rfx_2400_tx db_rfx_2400_tx = {
425 .base.output_enables = 0x00E0,
426 .base.used_pins = 0x00FF,
427 .base.freq_min = U2_DOUBLE_TO_FXPT_FREQ(2300e6),
428 .base.freq_max = U2_DOUBLE_TO_FXPT_FREQ(2900e6),
429 //.base.gain_min = U2_DOUBLE_TO_FXPT_GAIN(xxx),
430 //.base.gain_max = U2_DOUBLE_TO_FXPT_GAIN(xxx),
431 //.base.gain_step_size = U2_DOUBLE_TO_FXPT_GAIN(xxx),
432 .base.is_quadrature = true,
433 .base.i_and_q_swapped = false,
434 .base.spectrum_inverted = false,
435 .base.default_lo_offset = U2_DOUBLE_TO_FXPT_FREQ(12.5e6),
436 .base.init = rfx_init_tx,
437 .base.set_freq = rfx_set_freq,
438 .base.set_gain = rfx_set_gain_tx,
439 .base.set_tx_enable = rfx_set_tx_enable,
440 .base.atr_mask = 0x00E0,
441 .base.atr_txval = MIX_EN,
442 .base.atr_rxval = ANT_SW,
443 // .base.atr_tx_delay =
444 // .base.atr_rx_delay =
445 .base.set_antenna = 0,
449 .common.spi_mask = SPI_SS_TX_DB,
450 .common.freq_mult = 1
455 rfx_init_tx(struct db_base *dbb)
457 //struct db_rfx_dummy *db = (struct db_rfx_dummy *) dbb;
458 clocks_enable_tx_dboard(true, 0);
460 // Set the freq now to get the one time 10ms delay out of the way.
462 dbb->set_freq(dbb, dbb->freq_min, &dc);
467 rfx_init_rx(struct db_base *dbb)
469 //struct db_rfx_dummy *db = (struct db_rfx_dummy *) dbb;
470 clocks_enable_rx_dboard(true, 0);
473 dbb->set_gain(dbb,U2_DOUBLE_TO_FXPT_GAIN(45.0));
475 // Set the freq now to get the one time 10ms delay out of the way.
477 dbb->set_freq(dbb, dbb->freq_min, &dc);
483 rfx_set_freq(struct db_base *dbb, u2_fxpt_freq_t freq, u2_fxpt_freq_t *dc)
485 static unsigned char first = true;
488 struct db_rfx_dummy *db = (struct db_rfx_dummy *) dbb;
489 u2_fxpt_freq_t desired_n = (U2_DOUBLE_TO_FXPT_FREQ(1.0)*db->common.freq_mult*freq)/phdet_freq;
490 int N_DIV = u2_fxpt_freq_round_to_int(desired_n);
491 int B = N_DIV/PRESCALER;
492 int A = N_DIV - PRESCALER*B;
497 int R = (R_RSV<<22)|(R_BSC<<20)|(R_TMB<<19)|(R_LDP<<18)|(R_ABP<<16)|(R_DIV<<2)|1;
498 int N = (DIVSEL<<23)|(db->common.DIV2<<22)|(CPGAIN<<21)|(B<<8)|(N_RSV<<7)|(A<<2)|2;
499 int C = (P<<22)|(PD<<20)|(db->common.CP2<<17)|(db->common.CP1<<14)|(PL<<12)|
500 (MTLD<<11)|(CPGAIN<<10)|(CP3S<<9)|(PDP<<8)|(MUXOUT<<5)|(CR<<4)|(PC<<2)|0;
502 spi_transact(SPI_TXONLY,db->common.spi_mask,R,24,SPIF_PUSH_FALL);
503 spi_transact(SPI_TXONLY,db->common.spi_mask,C,24,SPIF_PUSH_FALL);
508 spi_transact(SPI_TXONLY,db->common.spi_mask,N,24,SPIF_PUSH_FALL);
510 //printf("A = %d, B = %d, N_DIV = %d\n",A, B, N_DIV);
511 *dc = (N_DIV * phdet_freq) / db->common.freq_mult;
516 rfx_set_gain_tx(struct db_base *dbb, u2_fxpt_gain_t gain)
518 // There is no analog gain control on TX
523 rfx_set_gain_rx(struct db_base *dbb, u2_fxpt_gain_t gain)
525 struct db_rfx_dummy *db = (struct db_rfx_dummy *) dbb;
527 int offset_q8 = (int)(1.2/3.3*4096*(1<<15));
528 int range_q15 = (int)(-1.0*4096/3.3*256*128);
529 int slope_q8 = range_q15/db->base.gain_max;
531 int dacword = ((slope_q8 * gain) + offset_q8)>>15;
532 //printf("DACWORD %d\n",dacword);
533 lsdac_write_rx(1,dacword);
539 rfx_set_tx_enable(struct db_base *dbb, bool on)
541 struct db_rfx_dummy *db = (struct db_rfx_dummy *) dbb;
549 rfx_lock_detect(struct db_base *dbb)
551 struct db_rfx_dummy *db = (struct db_rfx_dummy *) dbb;
553 pins = hal_gpio_read( db->base.is_tx ? GPIO_TX_BANK : GPIO_RX_BANK );
554 if(pins & LOCKDET_MASK)
560 def select_rx_antenna(self, which_antenna):
562 Specify which antenna port to use for reception.
563 @param which_antenna: either 'TX/RX' or 'RX2'
565 if which_antenna in (0, 'TX/RX'):
566 self._u.write_io(self._which, 0, RX2_RX1N)
567 elif which_antenna in (1, 'RX2'):
568 self._u.write_io(self._which, RX2_RX1N, RX2_RX1N)
570 raise ValueError, "which_antenna must be either 'TX/RX' or 'RX2'"
572 def set_gain(self, gain):
576 @param gain: gain in decibels
579 maxgain = self.gain_range()[1] - self._u.pga_max()
580 mingain = self.gain_range()[0]
582 pga_gain = gain-maxgain
583 assert pga_gain <= self._u.pga_max()
591 dac_value = (agc_gain*(V_maxgain-V_mingain)/(maxgain-mingain) + V_mingain)*4096/V_fullscale
592 assert dac_value>=0 and dac_value<4096
593 return self._u.write_aux_dac(self._which, 0, int(dac_value)) and \
594 self._set_pga(int(pga_gain))
596 def gain_range(self):
597 return (self._u.pga_min(), self._u.pga_max() + 70, 0.05) -- For 900-2400
598 return (self._u.pga_min(), self._u.pga_max() + 45, 0.035) -- For 400