3 * Copyright 2009 Free Software Foundation, Inc.
5 * This program is free software: you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation, either version 3 of the License, or
8 * (at your option) any later version.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program. If not, see <http://www.gnu.org/licenses/>.
22 #include <memory_map.h>
27 #define min(X,Y) ((X) < (Y) ? (X) : (Y))
28 #define max(X,Y) ((X) > (Y) ? (X) : (Y))
29 #define abs(X) ((X) < (0) ? ((-1)*(X)) : (X))
32 #define REFCLK_DIVISOR 25 // Gives a 4 MHz clock
33 #define REFCLK_FREQ U2_DOUBLE_TO_FXPT_FREQ(MASTER_CLK_RATE/REFCLK_DIVISOR)
34 #define REFCLK_FREQ_INT u2_fxpt_freq_round_to_int(REFCLK_FREQ)
40 #define DACFULLSCALE 3.3
42 bool db_dbsrx_init(struct db_base *db);
43 bool db_dbsrx_set_freq(struct db_base *db, u2_fxpt_freq_t freq, u2_fxpt_freq_t *dc);
44 bool db_dbsrx_set_gain(struct db_base *db, u2_fxpt_gain_t gain);
46 struct db_dbsrx_common {
61 struct db_dbsrx_dummy {
63 struct db_dbsrx_common common;
68 struct db_dbsrx_common common;
71 struct db_dbsrx db_dbsrx = {
74 .base.output_enables = 0x0000,
75 .base.used_pins = 0x0000,
76 .base.freq_min = U2_DOUBLE_TO_FXPT_FREQ(500e6),
77 .base.freq_max = U2_DOUBLE_TO_FXPT_FREQ(2.6e9),
78 .base.gain_min = U2_DOUBLE_TO_FXPT_GAIN(0),
79 .base.gain_max = U2_DOUBLE_TO_FXPT_GAIN(RFGAINMAX+BBGAINMAX),
80 .base.gain_step_size = U2_DOUBLE_TO_FXPT_GAIN(1),
81 .base.is_quadrature = true,
82 .base.i_and_q_swapped = false,
83 .base.spectrum_inverted = false,
84 .base.default_lo_offset = U2_DOUBLE_TO_FXPT_FREQ(0),
85 .base.init = db_dbsrx_init,
86 .base.set_freq = db_dbsrx_set_freq,
87 .base.set_gain = db_dbsrx_set_gain,
88 .base.set_tx_enable = 0,
89 .base.atr_mask = 0x0000,
92 //.base.atr_tx_delay =
93 //.base.atr_rx_delay =
109 db_dbsrx_init(struct db_base *dbb){
110 struct db_dbsrx_dummy *db = (struct db_dbsrx_dummy *) dbb;
111 db->base.set_gain(dbb, (db->base.gain_max + db->base.gain_min)/2);
112 clocks_enable_rx_dboard(true, REFCLK_DIVISOR); // Gives 4 MHz clock
117 /**************************************************
119 **************************************************/
122 unsigned char readback[2];
123 i2c_read(I2C_ADDR, readback, 2*sizeof(unsigned char));
124 int adc_val = (readback[0] >> 2)&7;
125 //printf("READBACK[0] %d, [1] %d\n",readback[0],readback[1]);
126 //printf("ADC: %d\n",adc_val);
131 _write_reg (int regno, int v){
132 //regno is in [0,5], v is value to write to register"""
133 unsigned char args[2];
134 args[0] = (unsigned char)regno;
135 args[1] = (unsigned char)v;
136 i2c_write(I2C_ADDR, args, 2*sizeof(unsigned char));
137 //printf("Reg %d, Val %x\n",regno,v);
140 static void _send_reg_0(struct db_dbsrx_dummy *db){
141 _write_reg(0,(db->common.d_div2<<7) + (db->common.d_n>>8));
144 static void _send_reg_1(struct db_dbsrx_dummy *db){
145 _write_reg(1,db->common.d_n & 255);
148 static void _send_reg_2(struct db_dbsrx_dummy *db){
149 _write_reg(2,db->common.d_osc + (db->common.d_cp<<3) + (db->common.d_r_reg<<5));
152 static void _send_reg_3(struct db_dbsrx_dummy *db){
153 _write_reg(3,db->common.d_fdac);
156 static void _send_reg_4(struct db_dbsrx_dummy *db){
157 _write_reg(4,db->common.d_m + (db->common.d_dl<<5) + (db->common.d_ade<<6) + (db->common.d_adl<<7));
160 static void _send_reg_5(struct db_dbsrx_dummy *db){
161 _write_reg(5,db->common.d_gc2 + (db->common.d_diag<<5));
164 /**************************************************
165 * Helpers for setting the freq
166 **************************************************/
168 _set_div2(struct db_dbsrx_dummy *db, int div2){
169 db->common.d_div2 = div2;
173 // FIXME How do we handle ADE and ADL properly?
175 _set_ade(struct db_dbsrx_dummy *db, int ade){
176 db->common.d_ade = ade;
181 _set_r(struct db_dbsrx_dummy *db, int r){
182 db->common.d_r_reg = r;
187 _set_n(struct db_dbsrx_dummy *db, int n){
194 _set_osc(struct db_dbsrx_dummy *db, int osc){
195 db->common.d_osc = osc;
200 _set_cp(struct db_dbsrx_dummy *db, int cp){
201 db->common.d_cp = cp;
205 /**************************************************
207 **************************************************/
211 db_dbsrx_set_freq(struct db_base *dbb, u2_fxpt_freq_t freq, u2_fxpt_freq_t *dc){
212 struct db_dbsrx_dummy *db = (struct db_dbsrx_dummy *) dbb;
214 if(!(freq>=db->base.freq_min && freq<=db->base.freq_max)) {
218 u2_fxpt_freq_t vcofreq;
219 if(freq < U2_DOUBLE_TO_FXPT_FREQ(1150e6)) {
229 int rmin = max(2, u2_fxpt_freq_round_to_int(REFCLK_FREQ/2e6)); //TODO? remove max()
230 //int rmax = min(128, u2_fxpt_freq_round_to_int(REFCLK_FREQ/500e3)); //TODO? remove min()
232 u2_fxpt_freq_t best_delta = U2_DOUBLE_TO_FXPT_FREQ(10e6);
233 u2_fxpt_freq_t delta;
236 while ((r_reg<7) && ((2<<r_reg) < rmin)) {
239 //printf ("r_reg = %d, r = %d\n",r_reg,2<<r_reg);
244 n = u2_fxpt_freq_round_to_int(freq/REFCLK_FREQ_INT*(2<<r_reg));
245 //printf("LOOP: r_reg %d, best_r %d, best_n %d, best_delta %d\n",
246 //r_reg,best_r,best_n,u2_fxpt_freq_round_to_int(best_delta));
248 //printf("N: %d\n",n);
253 delta = abs(n*REFCLK_FREQ/(2<<r_reg) - freq);
254 if(delta < best_delta) {
259 if(best_delta < U2_DOUBLE_TO_FXPT_FREQ(75e3)) {
265 //printf("BEST R: %d Best Delta %d Best N %d\n",
266 // best_r,u2_fxpt_freq_round_to_int(best_delta),best_n);
271 if(vcofreq < U2_DOUBLE_TO_FXPT_FREQ(2433e6))
273 else if(vcofreq < U2_DOUBLE_TO_FXPT_FREQ(2711e6))
275 else if(vcofreq < U2_DOUBLE_TO_FXPT_FREQ(3025e6))
277 else if(vcofreq < U2_DOUBLE_TO_FXPT_FREQ(3341e6))
279 else if(vcofreq < U2_DOUBLE_TO_FXPT_FREQ(3727e6))
281 else if(vcofreq < U2_DOUBLE_TO_FXPT_FREQ(4143e6))
283 else if(vcofreq < U2_DOUBLE_TO_FXPT_FREQ(4493e6))
287 //printf("Initial VCO choice %d\n",vco);
292 while(adc_val == 0 || adc_val == 7) {
293 adc_val = _read_adc();
294 //printf("adc %d\n",adc_val);
304 else if(adc_val == 7) {
315 if(adc_val == 1 || adc_val == 2) {
318 else if(adc_val == 3 || adc_val == 4) {
324 //printf("Final VCO choice %d\n",vco);
326 *dc = db->common.d_n * REFCLK_FREQ / (2<<db->common.d_r_reg);
331 /**************************************************
332 * Helpers for setting the gain
333 **************************************************/
336 _set_gc2(struct db_dbsrx_dummy *db, int gc2){
337 db->common.d_gc2 = gc2;
341 /**************************************************
343 **************************************************/
345 db_dbsrx_set_gain(struct db_base *dbb, u2_fxpt_gain_t gain){
346 struct db_dbsrx_dummy *db = (struct db_dbsrx_dummy *) dbb;
348 u2_fxpt_gain_t rfgain, bbgain;
350 if(!(gain >= db->base.gain_min && gain <= db->base.gain_max)) {
354 if(gain < U2_DOUBLE_TO_FXPT_GAIN(RFGAINMAX)) {
359 rfgain = U2_DOUBLE_TO_FXPT_GAIN(RFGAINMAX);
360 bbgain = gain - U2_DOUBLE_TO_FXPT_GAIN(RFGAINMAX);
363 int rf_gain_slope_q8 = 256 * 4096 * (VMAXGAIN-VMINGAIN) / RFGAINMAX / DACFULLSCALE;
364 int rf_gain_offset_q8 = 128 * 256 * 4096 * VMINGAIN / DACFULLSCALE;
366 int rfdac = (rfgain*rf_gain_slope_q8 + rf_gain_offset_q8)>>15;
368 //printf("Set RF Gain %d, %d\n",rfgain,rfdac);
369 lsdac_write_rx(1,rfdac);
372 int bb_gain_slope_q8 = 256*(0-31)/(BBGAINMAX-0);
374 int gc2 = u2_fxpt_gain_round_to_int((bb_gain_slope_q8 * bbgain)>>8) + 31;
375 //printf("Set BB Gain: %d, gc2 %d\n",bbgain,gc2);
382 /**************************************************
383 * Helpers for setting the bw
384 **************************************************/
386 _set_m(struct db_dbsrx_dummy *db, int m){
392 _set_fdac(struct db_dbsrx_dummy *db, int fdac){
393 db->common.d_fdac = fdac;