3 * Copyright 2007 Free Software Foundation, Inc.
5 * This program is free software: you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation, either version 3 of the License, or
8 * (at your option) any later version.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program. If not, see <http://www.gnu.org/licenses/>.
18 #ifndef INCLUDED_AD9777_REGS_H
19 #define INCLUDED_AD9777_REGS_H
21 #define R0_SW_RESET (1 << 5)
22 #define R0_SLEEP (1 << 4)
23 #define R0_POWER_DN (1 << 3)
24 #define R0_1R (1 << 2)
25 #define R0_2R (0 << 2)
26 #define R0_PLL_LOCKED (1 << 1)
28 #define R1_INTERP_1X 0x00
29 #define R1_INTERP_2X 0x40
30 #define R1_INTERP_4X 0x80
31 #define R1_INTERP_8X 0xC0
32 #define R1_MOD_NONE 0x00
33 #define R1_MOD_FS_2 0x10 // Fs/2
34 #define R1_MOD_FS_4 0x20 // Fs/4
35 #define R1_MOD_FS_8 0x30 // Fs/8
36 #define R1_ZERO_STUFF (1 << 3) // N.B., doubles output rate
37 #define R1_REAL_MIX (1 << 2)
38 #define R1_CMPLX_MIX (0 << 2)
39 #define R1_POS_EXP (1 << 1) // exp(+jwt)
40 #define R1_NEG_EXP (0 << 1) // exp(-jwt)
41 #define R1_DATACLK_OUT (1 << 0)
43 #define R2_2S_COMP (0 << 7)
44 #define R2_2PORT_MODE (0 << 6)
45 #define R2_1PORT_MODE (1 << 6)
47 #define R3_PLL_DIV_1 0x00
48 #define R3_PLL_DIV_2 0x01
49 #define R3_PLL_DIV_4 0x02
50 #define R3_PLL_DIV_8 0x03
52 #define R4_PLL_ON (1 << 7)
53 #define R4_CP_MANUAL (1 << 6)
54 #define R4_CP_AUTO (0 << 6)
55 #define R4_CP_50uA (0x00 | R4_CP_MANUAL)
56 #define R4_CP_100uA (0x01 | R4_CP_MANUAL)
57 #define R4_CP_200uA (0x02 | R4_CP_MANUAL)
58 #define R4_CP_400uA (0x03 | R4_CP_MANUAL)
59 #define R4_CP_800uA (0x07 | R4_CP_MANUAL)
61 #define R5_I_FINE_GAIN(g) (g) // 8-bits
62 #define R6_I_COARSE_GAIN(g) ((g) & 0xf) // low 4-bits
64 #define R9_Q_FINE_GAIN(g) (g) // 8-bits
65 #define R10_Q_COARSE_GAIN(g) ((g) & 0xf) // low 4-bits
68 // FIXME more registers for offset and gain control...
71 #endif /* INCLUDED_AD9777_REGS_H */