3 * Copyright 2007 Free Software Foundation, Inc.
5 * This program is free software: you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation, either version 3 of the License, or
8 * (at your option) any later version.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program. If not, see <http://www.gnu.org/licenses/>.
19 #ifndef INCLUDED_USRP2_FPGA_REGS_H
20 #define INCLUDED_USSRP2_FPGA_REGS_H
22 #include "usrp2_cdefs.h"
26 // ----------------------------------------------------------------
28 #define DSP_CORE_TX_BASE 128
30 // DUC center frequency tuning word (phase increment)
31 #define FR_TX_FREQ_0 (0 + DSP_CORE_TX_BASE)
33 // I & Q output scaling, 16.0 format ((I_SCALE << 16) | Q_SCALE)
34 #define FR_TX_SCALE_0 (1 + DSP_CORE_TX_BASE)
36 // Tx interpolation rate (set to 1 less than desired rate)
37 #define FR_TX_INTERP_RATE_0 (2 + DSP_CORE_TX_BASE)
39 // Write 1 (actually anything) to clear tx state
40 #define FR_TX_CLEAR_STATE_0 (3 + DSP_CORE_TX_BASE)
42 // ----------------------------------------------------------------
44 #define DSP_CORE_RX_BASE 160
46 // DDC center frequency tuning word (phase increment)
47 #define FR_RX_FREQ_0 (0 + DSP_CORE_RX_BASE)
49 // I & Q input scaling, 16.0 format ((I_SCALE << 16) | Q_SCALE)
50 #define FR_RX_SCALE_0 (1 + DSP_CORE_RX_BASE)
52 // Rx decimation rate (set to 1 less than desired rate)
53 #define FR_RX_DECIM_RATE_0 (2 + DSP_CORE_RX_BASE)
55 // The next two registers concatenated are the Rx command register.
57 // Writing FR_RX_TIME_TO_RX_0 writes the concatenated value into the
58 // cmd queue. Thus, if you're writing both, be sure to write
61 // +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
63 // +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
65 #define FR_RX_TIME_TO_RX (3 + DSP_CORE_RX_BASE)
68 // +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
69 // | number_of_lines | lines_per_frame |
70 // +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
72 #define FR_RX_QTY_0 (4 + DSP_CORE_RX_BASE)
74 // write a 1 (anything actually) to clear the overrun
75 #define FR_RX_CLR_OVERRUN_0 (5 + DSP_CORE_RX_BASE)
80 #endif /* INCLUDED_USRP2_FPGA_REGS_H */