3 * Copyright 2007,2008,2009,2010 Free Software Foundation, Inc.
5 * This program is free software: you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation, either version 3 of the License, or
8 * (at your option) any later version.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program. If not, see <http://www.gnu.org/licenses/>.
19 #ifndef INCLUDED_USRP2_ETH_PACKET_H
20 #define INCLUDED_USRP2_ETH_PACKET_H
22 #include "usrp2_cdefs.h"
23 #include "usrp2_bytesex.h"
24 #include "usrp2_mac_addr.h"
25 #include "usrp2_mimo_config.h"
29 #define U2_ETHERTYPE 0xBEEF // used in our frames
30 #define MAC_CTRL_ETHERTYPE 0x8808 // used in PAUSE frames
33 * All these data structures are BIG-ENDIAN on the wire
36 // FIXME gcc specific. Really ought to come from compiler.h
37 #define _AL4 __attribute__((aligned (4)))
40 * \brief The classic 14-byte ethernet header
46 } __attribute__((packed)) u2_eth_hdr_t;
49 * \brief USRP2 transport header
51 * This enables host->usrp2 flow control and dropped packet detection.
54 uint16_t flags; // MBZ, may be used for channel in future
55 uint16_t fifo_status; // free space in Rx fifo in 32-bit lines
56 uint8_t seqno; // sequence number of this packet
57 uint8_t ack; // sequence number of next packet expected
58 } __attribute__((packed)) u2_transport_hdr_t;
62 * The fixed payload header of a USRP2 ethernet packet...
64 * Basically there's 1 word of flags and routing info, and 1 word
65 * of timestamp that specifies when the data was received, or
66 * when it should be transmitted. The data samples follow immediately.
68 * Transmit packets (from host to U2)
70 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
71 * | Chan | mbz |I|S|E|
72 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
74 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
77 * Received packets (from U2 to host)
79 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
81 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
83 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
89 uint32_t word0; // flags etc
90 uint32_t timestamp; // time of rx or tx (100 MHz)
94 #define U2P_CHAN_MASK 0x1f
95 #define U2P_CHAN_SHIFT 27
97 #define U2P_TX_IMMEDIATE 0x00000004 // send samples NOW, else at timestamp
98 #define U2P_TX_START_OF_BURST 0x00000002 // this frame is the start of a burst
99 #define U2P_TX_END_OF_BURST 0x00000001 // this frame is the end of a burst
101 #define U2P_ALL_FLAGS 0x00000007
103 #define CONTROL_CHAN 0x1f
106 u2p_chan(u2_fixed_hdr_t *p)
108 return (ntohl(p->word0) >> U2P_CHAN_SHIFT) & U2P_CHAN_MASK;
111 inline static uint32_t
112 u2p_word0(u2_fixed_hdr_t *p)
114 return ntohl(p->word0);
117 inline static uint32_t
118 u2p_timestamp(u2_fixed_hdr_t *p)
120 return ntohl(p->timestamp);
124 u2p_set_word0(u2_fixed_hdr_t *p, int flags, int chan)
126 p->word0 = htonl((flags & U2P_ALL_FLAGS)
127 | ((chan & U2P_CHAN_MASK) << U2P_CHAN_SHIFT));
131 u2p_set_timestamp(u2_fixed_hdr_t *p, uint32_t ts)
133 p->timestamp = htonl(ts);
137 * \brief consolidated packet: ethernet header + transport header + fixed header
141 u2_transport_hdr_t thdr;
142 u2_fixed_hdr_t fixed;
146 * full load of samples:
147 * ethernet header + transport header + fixed header + maximum number of samples.
148 * sizeof(u2_eth_samples_t) == 1512
149 * (payload is 1498 bytes, two bytes shorter than 1500 byte MTU)
150 * (sample numbers are made even to force pairwise alignment in the interleaved case)
153 #define U2_MAX_SAMPLES 370
154 #define U2_MIN_SAMPLES 10
157 u2_eth_packet_t hdrs;
158 uint32_t samples[U2_MAX_SAMPLES];
162 * Opcodes for control channel
164 * Reply opcodes are the same as the request opcode with the OP_REPLY_BIT set (0x80).
166 #define OP_REPLY_BIT 0x80
168 #define OP_EOP 0 // marks last subpacket in packet
171 #define OP_ID_REPLY (OP_ID | OP_REPLY_BIT)
172 #define OP_BURN_MAC_ADDR 2
173 #define OP_BURN_MAC_ADDR_REPLY (OP_BURN_MAC_ADDR | OP_REPLY_BIT)
174 #define OP_READ_TIME 3 // What time is it? (100 MHz counter)
175 #define OP_READ_TIME_REPLY (OP_READ_TIME | OP_REPLY_BIT)
176 #define OP_CONFIG_RX_V2 4
177 #define OP_CONFIG_RX_REPLY_V2 (OP_CONFIG_RX_V2 | OP_REPLY_BIT)
178 #define OP_CONFIG_TX_V2 5
179 #define OP_CONFIG_TX_REPLY_V2 (OP_CONFIG_TX_V2 | OP_REPLY_BIT)
180 #define OP_START_RX_STREAMING 6
181 #define OP_START_RX_STREAMING_REPLY (OP_START_RX_STREAMING | OP_REPLY_BIT)
183 #define OP_STOP_RX_REPLY (OP_STOP_RX | OP_REPLY_BIT)
184 #define OP_CONFIG_MIMO 8
185 #define OP_CONFIG_MIMO_REPLY (OP_CONFIG_MIMO | OP_REPLY_BIT)
186 #define OP_DBOARD_INFO 9
187 #define OP_DBOARD_INFO_REPLY (OP_DBOARD_INFO | OP_REPLY_BIT)
188 #define OP_SYNC_TO_PPS 10
189 #define OP_SYNC_TO_PPS_REPLY (OP_SYNC_TO_PPS | OP_REPLY_BIT)
191 #define OP_PEEK_REPLY (OP_PEEK | OP_REPLY_BIT)
193 #define OP_POKE_REPLY (OP_POKE | OP_REPLY_BIT)
194 #define OP_SET_TX_LO_OFFSET 13
195 #define OP_SET_TX_LO_OFFSET_REPLY (OP_SET_TX_LO_OFFSET | OP_REPLY_BIT)
196 #define OP_SET_RX_LO_OFFSET 14
197 #define OP_SET_RX_LO_OFFSET_REPLY (OP_SET_RX_LO_OFFSET | OP_REPLY_BIT)
198 #define OP_RESET_DB 15
199 #define OP_RESET_DB_REPLY (OP_RESET_DB | OP_REPLY_BIT)
200 #define OP_SYNC_EVERY_PPS 16
201 #define OP_SYNC_EVERY_PPS_REPLY (OP_SYNC_EVERY_PPS | OP_REPLY_BIT)
202 #define OP_GPIO_SET_DDR 17
203 #define OP_GPIO_SET_DDR_REPLY (OP_GPIO_SET_DDR | OP_REPLY_BIT)
204 #define OP_GPIO_SET_SELS 18
205 #define OP_GPIO_SET_SELS_REPLY (OP_GPIO_SET_SELS | OP_REPLY_BIT)
206 #define OP_GPIO_READ 19
207 #define OP_GPIO_READ_REPLY (OP_GPIO_READ | OP_REPLY_BIT)
208 #define OP_GPIO_WRITE 20
209 #define OP_GPIO_WRITE_REPLY (OP_GPIO_WRITE | OP_REPLY_BIT)
210 #define OP_GPIO_STREAM 21
211 #define OP_GPIO_STREAM_REPLY (OP_GPIO_STREAM | OP_REPLY_BIT)
212 #define OP_RX_ANTENNA 22
213 #define OP_RX_ANTENNA_REPLY (OP_RX_ANTENNA | OP_REPLY_BIT)
214 #define OP_TX_ANTENNA 23
215 #define OP_TX_ANTENNA_REPLY (OP_RX_ANTENNA | OP_REPLY_BIT)
218 * All subpackets are a multiple of 4 bytes long.
219 * All subpackets start with an 8-bit opcode, an 8-bit len and an 8-bit rid.
221 #define MAX_SUBPKT_LEN 252
224 * \brief Generic request and reply packet
227 * OP_EOP, OP_BURN_MAC_ADDR_REPLY, OP_START_RX_STREAMING_REPLY,
228 * OP_STOP_RX_REPLY, OP_DBOARD_INFO, OP_SYNC_TO_PPS
238 * \brief Reply info from a USRP2
247 uint8_t fpga_md5sum[16];
248 uint8_t sw_md5sum[16];
249 } _AL4 op_id_reply_t;
256 uint32_t items_per_frame; // # of 32-bit data items; MTU=1500: [9,371]
257 } _AL4 op_start_rx_streaming_t;
264 } _AL4 op_burn_mac_addr_t;
272 } _AL4 op_read_time_reply_t;
276 * \brief Configure receiver
283 // bitmask indicating which of the following fields are valid
285 uint16_t gain; // fxpt_db (Q9.7)
286 uint32_t freq_hi; // high 32-bits of 64-bit fxpt_freq (Q44.20)
287 uint32_t freq_lo; // low 32-bits of 64-bit fxpt_freq (Q44.20)
288 uint32_t decim; // desired decimation factor (NOT -1)
289 uint32_t scale_iq; // (scale_i << 16) | scale_q [16.0 format]
290 } _AL4 op_config_rx_v2_t;
292 // bitmask for "valid" field. If the bit is set, there's
293 // meaningful data in the corresonding field.
295 #define CFGV_GAIN 0x0001 // gain field is valid
296 #define CFGV_FREQ 0x0002 // target_freq field is valid
297 #define CFGV_INTERP_DECIM 0x0004 // interp or decim is valid
298 #define CFGV_SCALE_IQ 0x0008 // scale_iq is valid
301 * \brief Reply to receiver configuration
309 uint16_t ok; // config was successful (bool)
310 uint16_t inverted; // spectrum is inverted (bool)
312 // RF frequency that corresponds to DC in the IF (fxpt_freq)
313 uint32_t baseband_freq_hi;
314 uint32_t baseband_freq_lo;
315 // DDC frequency (fxpt_freq)
316 uint32_t ddc_freq_hi;
317 uint32_t ddc_freq_lo;
318 // residual frequency (fxpt_freq)
319 uint32_t residual_freq_hi;
320 uint32_t residual_freq_lo;
322 } _AL4 op_config_rx_reply_v2_t;
325 * \brief Configure transmitter
333 // bitmask indicating which of the following fields are valid
335 uint16_t gain; // fxpt_db (Q9.7)
336 uint32_t freq_hi; // high 32-bits of 64-bit fxpt_freq (Q44.20)
337 uint32_t freq_lo; // low 32-bits of 64-bit fxpt_freq (Q44.20)
338 uint32_t interp; // desired interpolation factor (NOT -1)
339 uint32_t scale_iq; // (scale_i << 16) | scale_q [16.0 format]
340 } _AL4 op_config_tx_v2_t;
343 * \brief Reply to configure transmitter
351 uint16_t ok; // config was successful (bool)
352 uint16_t inverted; // spectrum is inverted (bool)
354 // RF frequency that corresponds to DC in the IF (fxpt_freq)
355 uint32_t baseband_freq_hi;
356 uint32_t baseband_freq_lo;
357 // DUC frequency (fxpt_freq)
358 uint32_t duc_freq_hi;
359 uint32_t duc_freq_lo;
360 // residual frequency (fxpt_freq)
361 uint32_t residual_freq_hi;
362 uint32_t residual_freq_lo;
364 } _AL4 op_config_tx_reply_v2_t;
367 * \brief Configure MIMO clocking, etc (uses generic reply)
373 uint8_t flags; // from usrp_mimo_config.h
378 * \brief High-level information about daughterboards
381 int32_t dbid; //< d'board ID (-1 none, -2 invalid eeprom)
382 uint32_t freq_min_hi; //< high 32-bits of 64-bit fxpt_freq (Q44.20)
383 uint32_t freq_min_lo; //< low 32-bits of 64-bit fxpt_freq (Q44.20)
384 uint32_t freq_max_hi; //< high 32-bits of 64-bit fxpt_freq (Q44.20)
385 uint32_t freq_max_lo; //< low 32-bits of 64-bit fxpt_freq (Q44.20)
386 uint16_t gain_min; //< min gain that can be set. fxpt_db (Q9.7)
387 uint16_t gain_max; //< max gain that can be set. fxpt_db (Q9.7)
388 uint16_t gain_step_size; //< fxpt_db (Q9.7)
393 * \brief Reply to d'board info request
399 uint8_t ok; // request was successful (bool)
401 u2_db_info_t tx_db_info;
402 u2_db_info_t rx_db_info;
403 } _AL4 op_dboard_info_reply_t;
406 * \brief Read from Wishbone memory
418 * \brief Write to Wishbone memory
430 * Common structure for commands with a single frequency param
431 * (e.g., set_*_lo_offset, set_*_bw)
438 uint32_t freq_hi; //< high 32-bits of 64-bit fxpt_freq (Q44.20)
439 uint32_t freq_lo; //< low 32-bits of 64-bit fxpt_freq (Q44.20)
443 * Structures for commands in GPIO system
446 uint8_t opcode; // OP_GPIO_SET_DDR, OP_GPIO_WRITE, OP_GPIO_STREAM
455 uint8_t opcode; // OP_GPIO_SET_SELS
460 } _AL4 op_gpio_set_sels_t;
463 uint8_t opcode; // OP_GPIO_READ_REPLY
469 } _AL4 op_gpio_read_reply_t;
472 * ================================================================
473 * union of all of subpacket types
474 * ================================================================
478 op_generic_t op_generic;
479 op_id_reply_t op_id_reply;
480 op_start_rx_streaming_t op_start_rx_streaming;
481 op_burn_mac_addr_t op_burn_mac_addr;
482 op_read_time_reply_t op_read_time_reply;
483 op_config_rx_v2_t op_config_rx_v2;
484 op_config_rx_reply_v2_t op_config_rx_reply_v2;
485 op_config_tx_v2_t op_config_tx_v2;
486 op_config_tx_reply_v2_t op_config_tx_reply_v2;
487 op_config_mimo_t op_config_mimo;
492 op_gpio_set_sels_t op_gpio_set_sels;
493 op_gpio_read_reply_t op_gpio_read_reply;
500 #endif /* INCLUDED_USRP2_ETH_PACKET_H */