2 * Copyright 2007,2008 Free Software Foundation, Inc.
4 * This program is free software: you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation, either version 3 of the License, or
7 * (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
14 * You should have received a copy of the GNU General Public License
15 * along with this program. If not, see <http://www.gnu.org/licenses/>.
23 #include "memory_map.h"
26 #include "buffer_pool.h"
31 #include "usrp2_eth_packet.h"
33 #include "app_common_v2.h"
34 #include "memcpy_wa.h"
40 #define FW_SETS_SEQNO 1 // define to 0 or 1 (FIXME must be 1 for now)
43 static int fw_seqno; // used when f/w is filling in sequence numbers
48 * Full duplex Tx and Rx between ethernet and DSP pipelines
50 * Buffer 1 is used by the cpu to send frames to the host.
51 * Buffers 2 and 3 are used to double-buffer the DSP Rx to eth flow
52 * Buffers 4 and 5 are used to double-buffer the eth to DSP Tx eth flow
54 //#define CPU_RX_BUF 0 // eth -> cpu
56 #define DSP_RX_BUF_0 2 // dsp rx -> eth (double buffer)
57 #define DSP_RX_BUF_1 3 // dsp rx -> eth
58 #define DSP_TX_BUF_0 4 // eth -> dsp tx (double buffer)
59 #define DSP_TX_BUF_1 5 // eth -> dsp tx
62 * ================================================================
63 * configure DSP TX double buffering state machine (eth -> dsp)
64 * ================================================================
67 // 4 lines of ethernet hdr + 1 line transport hdr + 2 lines (word0 + timestamp)
68 // DSP Tx reads word0 (flags) + timestamp followed by samples
70 #define DSP_TX_FIRST_LINE ((sizeof(u2_eth_hdr_t) + sizeof(u2_transport_hdr_t))/4)
72 // Receive from ethernet
73 buf_cmd_args_t dsp_tx_recv_args = {
80 buf_cmd_args_t dsp_tx_send_args = {
82 DSP_TX_FIRST_LINE, // starts just past transport header
83 0 // filled in from last_line register
86 dbsm_t dsp_tx_sm; // the state machine
89 * ================================================================
90 * configure DSP RX double buffering state machine (dsp -> eth)
91 * ================================================================
94 // 4 lines of ethernet hdr + 1 line transport hdr + 1 line (word0)
95 // DSP Rx writes timestamp followed by nlines_per_frame of samples
96 #define DSP_RX_FIRST_LINE ((sizeof(u2_eth_hdr_t) + sizeof(u2_transport_hdr_t))/4 + 1)
99 buf_cmd_args_t dsp_rx_recv_args = {
106 buf_cmd_args_t dsp_rx_send_args = {
108 0, // starts with ethernet header in line 0
109 0, // filled in from list_line register
112 dbsm_t dsp_rx_sm; // the state machine
115 // The mac address of the host we're sending to.
116 u2_mac_addr_t host_mac_addr;
119 // variables for streaming mode
121 static bool streaming_p = false;
122 static unsigned int streaming_items_per_frame = 0;
123 static int streaming_frame_count = 0;
124 #define FRAMES_PER_CMD 1000
127 // ----------------------------------------------------------------
131 restart_streaming(void)
134 dsp_rx_regs->clear_state = 1; // reset
137 streaming_frame_count = FRAMES_PER_CMD;
139 dsp_rx_regs->rx_command =
140 MK_RX_CMD(FRAMES_PER_CMD * streaming_items_per_frame,
141 streaming_items_per_frame,
142 1, 1); // set "chain" bit
144 // kick off the state machine
145 dbsm_start(&dsp_rx_sm);
147 dsp_rx_regs->rx_time = 0; // enqueue first of two commands
149 // make sure this one and the rest have the "now" and "chain" bits set.
150 dsp_rx_regs->rx_command =
151 MK_RX_CMD(FRAMES_PER_CMD * streaming_items_per_frame,
152 streaming_items_per_frame,
155 dsp_rx_regs->rx_time = 0; // enqueue second command
159 start_rx_streaming_cmd(const u2_mac_addr_t *host, op_start_rx_streaming_t *p)
161 host_mac_addr = *host; // remember who we're sending to
164 * Construct ethernet header and word0 and preload into two buffers
167 memset(&pkt, 0, sizeof(pkt));
168 pkt.ehdr.dst = *host;
169 pkt.ehdr.ethertype = U2_ETHERTYPE;
170 u2p_set_word0(&pkt.fixed, 0, 0);
171 // DSP RX will fill in timestamp
173 memcpy_wa(buffer_ram(DSP_RX_BUF_0), &pkt, sizeof(pkt));
174 memcpy_wa(buffer_ram(DSP_RX_BUF_1), &pkt, sizeof(pkt));
180 streaming_items_per_frame = p->items_per_frame;
189 dsp_rx_regs->clear_state = 1; // flush cmd queue
190 bp_clear_buf(DSP_RX_BUF_0);
191 bp_clear_buf(DSP_RX_BUF_1);
198 dsp_tx_regs->clear_state = 1;
199 bp_clear_buf(DSP_TX_BUF_0);
200 bp_clear_buf(DSP_TX_BUF_1);
205 // setup some defaults
207 dsp_tx_regs->freq = 0;
208 dsp_tx_regs->scale_iq = (tx_scale << 16) | tx_scale;
209 dsp_tx_regs->interp_rate = interp;
215 * Debugging ONLY. This will be handled by the tx_protocol_engine.
217 * This is called when the DSP Rx chain has filled in a packet.
218 * We set and increment the seqno, then return false, indicating
219 * that we didn't handle the packet. A bit of a kludge
220 * but it should work.
223 fw_sets_seqno_inspector(dbsm_t *sm, int buf_this) // returns false
225 uint32_t *p = buffer_ram(buf_this);
226 uint32_t seqno = fw_seqno++;
228 // KLUDGE all kinds of nasty magic numbers and embedded knowledge
230 t = (t & 0xffff00ff) | ((seqno & 0xff) << 8);
233 // queue up another rx command when required
234 if (streaming_p && --streaming_frame_count == 0){
235 streaming_frame_count = FRAMES_PER_CMD;
236 dsp_rx_regs->rx_time = 0;
239 return false; // we didn't handle the packet
245 buffer_irq_handler(unsigned irq)
247 uint32_t status = buffer_pool_status->status;
249 dbsm_process_status(&dsp_tx_sm, status);
250 dbsm_process_status(&dsp_rx_sm, status);
259 print_mac_addr(ethernet_mac_addr()->addr);
262 ethernet_register_link_changed_callback(link_changed_callback);
267 // make bit 15 of Tx gpio's be a s/w output
268 hal_gpio_set_sel(GPIO_TX_BANK, 15, 's');
269 hal_gpio_set_ddr(GPIO_TX_BANK, 0x8000, 0x8000);
272 output_regs->debug_mux_ctrl = 1;
274 hal_gpio_set_sels(GPIO_TX_BANK, "1111111111111111");
275 hal_gpio_set_sels(GPIO_RX_BANK, "1111111111111111");
276 hal_gpio_set_ddr(GPIO_TX_BANK, 0xffff, 0xffff);
277 hal_gpio_set_ddr(GPIO_RX_BANK, 0xffff, 0xffff);
281 // initialize double buffering state machine for ethernet -> DSP Tx
283 dbsm_init(&dsp_tx_sm, DSP_TX_BUF_0,
284 &dsp_tx_recv_args, &dsp_tx_send_args,
288 // initialize double buffering state machine for DSP RX -> Ethernet
291 dbsm_init(&dsp_rx_sm, DSP_RX_BUF_0,
292 &dsp_rx_recv_args, &dsp_rx_send_args,
293 fw_sets_seqno_inspector);
296 dbsm_init(&dsp_rx_sm, DSP_RX_BUF_0,
297 &dsp_rx_recv_args, &dsp_rx_send_args,
301 // tell app_common that this dbsm could be sending to the ethernet
302 ac_could_be_sending_to_eth = &dsp_rx_sm;
305 // program tx registers
308 // kick off the state machine
309 dbsm_start(&dsp_tx_sm);
314 // hal_gpio_write(GPIO_TX_BANK, which, 0x8000);
317 buffer_irq_handler(0);
319 int pending = pic_regs->pending; // poll for under or overrun
321 if (pending & PIC_UNDERRUN_INT){
322 dbsm_handle_tx_underrun(&dsp_tx_sm);
323 pic_regs->pending = PIC_UNDERRUN_INT; // clear interrupt
327 if (pending & PIC_OVERRUN_INT){
328 dbsm_handle_rx_overrun(&dsp_rx_sm);
329 pic_regs->pending = PIC_OVERRUN_INT; // clear pending interrupt
331 // FIXME Figure out how to handle this robustly.
332 // Any buffers that are emptying should be allowed to drain...
335 // restart_streaming();
336 // FIXME report error
339 // FIXME report error