2 * Copyright 2007,2008 Free Software Foundation, Inc.
4 * This program is free software: you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation, either version 3 of the License, or
7 * (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
14 * You should have received a copy of the GNU General Public License
15 * along with this program. If not, see <http://www.gnu.org/licenses/>.
23 #include "memory_map.h"
26 #include "buffer_pool.h"
31 #include "usrp2_eth_packet.h"
33 #include "app_common.h"
40 * This program can respond to queries from the host
41 * and stream rx samples.
43 * Buffer 1 is used by the cpu to send frames to the host.
44 * Buffers 2 and 3 are used to double-buffer the DSP Rx to eth flow
45 * Buffers 4 and 5 are used to double-buffer the eth to DSP Tx eth flow
47 //#define CPU_RX_BUF 0 // eth -> cpu
48 //#define CPU_TX_BUF 1 // cpu -> eth
50 #define DSP_RX_BUF_0 2 // dsp rx -> eth (double buffer)
51 #define DSP_RX_BUF_1 3 // dsp rx -> eth
52 #define DSP_TX_BUF_0 4 // eth -> dsp tx (double buffer)
53 #define DSP_TX_BUF_1 5 // eth -> dsp tx
56 * ================================================================
57 * configure DSP TX double buffering state machine
58 * ================================================================
61 // 4 lines of ethernet hdr + 1 line transport hdr + 2 lines (word0 + timestamp)
62 // DSP Tx reads word0 (flags) + timestamp followed by samples
64 #define DSP_TX_FIRST_LINE ((sizeof(u2_eth_hdr_t) + sizeof(u2_transport_hdr_t))/4)
66 // Receive from ethernet
67 buf_cmd_args_t dsp_tx_recv_args = {
74 buf_cmd_args_t dsp_tx_send_args = {
76 DSP_TX_FIRST_LINE, // starts just past transport header
77 0 // filled in from last_line register
80 dbsm_t dsp_tx_sm; // the state machine
83 // ----------------------------------------------------------------
86 // The mac address of the host we're sending to.
87 u2_mac_addr_t host_mac_addr;
91 start_rx_cmd(const u2_mac_addr_t *host, op_start_rx_t *p)
103 dsp_tx_regs->clear_state = 1;
104 bp_clear_buf(DSP_TX_BUF_0);
105 bp_clear_buf(DSP_TX_BUF_1);
110 op_config_tx_t def_config;
111 memset(&def_config, 0, sizeof(def_config));
112 def_config.phase_inc = 408021893; // 9.5 MHz [2**32 * fc/fsample]
113 def_config.scale_iq = (tx_scale << 16) | tx_scale;
114 def_config.interp = interp;
117 config_tx_cmd(&def_config);
122 buffer_irq_handler(unsigned irq)
124 //hal_toggle_leds(0x2);
126 uint32_t status = buffer_pool_status->status;
128 dbsm_process_status(&dsp_tx_sm, status);
130 if (status & BPS_DONE(CPU_TX_BUF)){
131 bp_clear_buf(CPU_TX_BUF);
140 // Get our clock from the mimo interface
142 clocks_enable_test_clk(true,1);
143 clocks_mimo_config(MC_WE_LOCK_TO_MIMO);
145 // setup tx gpio bits for GPIOM_FPGA_1 -- fpga debug output
146 //hal_gpio_set_sels(GPIO_TX_BANK, "1111111111111111");
147 //hal_gpio_set_sels(GPIO_RX_BANK, "1111111111111111");
149 putstr("\nserdes_to_dsp\n");
151 ethernet_register_link_changed_callback(link_changed_callback);
155 // initialize double buffering state machine for ethernet -> DSP Tx
157 dbsm_init(&dsp_tx_sm, DSP_TX_BUF_0,
158 &dsp_tx_recv_args, &dsp_tx_send_args,
161 // program tx registers
164 // kick off the state machine
165 dbsm_start(&dsp_tx_sm);
168 buffer_irq_handler(0);
170 int pending = pic_regs->pending; // poll for under or overrun
172 if (pending & PIC_UNDERRUN_INT){
173 dbsm_handle_tx_underrun(&dsp_tx_sm);
174 pic_regs->pending = PIC_UNDERRUN_INT; // clear interrupt