2 * Copyright 2007,2008 Free Software Foundation, Inc.
4 * This program is free software: you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation, either version 3 of the License, or
7 * (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
14 * You should have received a copy of the GNU General Public License
15 * along with this program. If not, see <http://www.gnu.org/licenses/>.
22 #include "memory_map.h"
25 #include "buffer_pool.h"
29 #include "memset_wa.h"
36 // ----------------------------------------------------------------
38 int packet_number = 0;
39 volatile bool send_packet_now = 0;
41 #define SERDES_TX_BUF 0
42 #define SERDES_RX_BUF 1
45 #define NLINES_PER_PKT 380
48 // ----------------------------------------------------------------
50 //static int timer_delta = (int)(MASTER_CLK_RATE * 100e-6);
51 static int timer_delta = 1000000; // .01 second
54 timer_irq_handler(unsigned irq)
56 hal_set_timeout(timer_delta); // schedule next timeout
57 send_packet_now = true;
65 for (i = 0; i < BP_NLINES; i++){
66 buf[i] = ((2*i + 0) << 16) | (2*i+1);
71 check_packet(int *buf, int nlines)
75 for (i = 0; i < nlines; i++){
76 int expected = ((2*i + 0) << 16) | (2*i+1);
77 if (buf[i] != expected){
79 printf("buf[%d] = 0x%x expected = 0x%x\n", i, buf[i], expected);
86 zero_buffer(int bufno)
88 memset_wa(buffer_ram(bufno), 0, BP_NLINES * 4);
94 // init just the one we're using
95 init_packet(buffer_ram(SERDES_TX_BUF));
103 // We're free running and provide clock to the MIMO interface
104 clocks_mimo_config(MC_WE_DONT_LOCK | MC_PROVIDE_CLK_TO_MIMO);
107 // setup tx gpio bits for GPIOM_FPGA_1 -- fpga debug output
108 // output_regs->debug_mux_ctrl = 1;
109 // hal_gpio_set_sels(GPIO_TX_BANK, "1111111111111111");
110 // hal_gpio_set_sels(GPIO_RX_BANK, "1111111111111111");
112 putstr("\nsd_gentest\n");
114 // Set up serdes (already enabled)
115 //output_regs->serdes_ctrl = (SERDES_ENABLE | SERDES_RXEN | SERDES_LOOPEN);
116 //output_regs->serdes_ctrl = (SERDES_ENABLE | SERDES_RXEN);
120 // pic_register_handler(IRQ_TIMER, timer_irq_handler);
122 //if (hwconfig_simulation_p())
123 // timer_delta = sim_timer_delta;
125 // start a receive from sd
126 zero_buffer(SERDES_RX_BUF);
127 bp_receive_to_buf(SERDES_RX_BUF, PORT_SERDES, 1, 0, BP_LAST_LINE);
129 // fire off the first packet
130 bp_send_from_buf(SERDES_TX_BUF, PORT_SERDES, 1, 0, NLINES_PER_PKT);
131 hal_set_timeout(timer_delta);
132 int ready_to_send = 0;
134 int counter __attribute__((unused)) = 0;
146 #define EXPECTING_PKT() ((counter & 0x1) == 0)
147 #define SEND_PKT() ((counter & 0x1) != 0)
149 bool got_packet = false;
152 uint32_t status = buffer_pool_status->status;
154 if (status & (BPS_DONE(SERDES_RX_BUF))){
155 bp_clear_buf(SERDES_RX_BUF);
158 //hal_toggle_leds(0x2);
161 int last_line = buffer_pool_status->last_line[SERDES_RX_BUF]-1;
162 bool ok = check_packet(buffer_ram(SERDES_RX_BUF), last_line);
173 // start a receive from sd
174 zero_buffer(SERDES_RX_BUF);
175 bp_receive_to_buf(SERDES_RX_BUF, PORT_SERDES, 1, 0, BP_LAST_LINE);
178 if (status & (BPS_ERROR(SERDES_RX_BUF))){
179 bp_clear_buf(SERDES_RX_BUF);
185 // start a receive from sd
186 zero_buffer(SERDES_RX_BUF);
187 bp_receive_to_buf(SERDES_RX_BUF, PORT_SERDES, 1, 0, BP_LAST_LINE);
190 if (status & (BPS_DONE(SERDES_TX_BUF))){
191 bp_clear_buf(SERDES_TX_BUF);
193 bp_send_from_buf(SERDES_TX_BUF, PORT_SERDES, 1, 0, NLINES_PER_PKT);
196 for (i = 0; i < 50; i++){
197 asm volatile ("or r0, r0, r0\n\
207 //hal_toggle_leds(0x1);
210 if (status & BPS_ERROR(SERDES_TX_BUF)){
211 bp_clear_buf(SERDES_TX_BUF);
219 printf("Status\tSENT %d\tTXERR %d\t",sent,txerr);
220 printf("RX %d\tERR %d\tCRC %d\tMISSED %d\n",rcvd, rxerr, rxcrc, sent-rcvd);
221 sent_acc += sent; sent = 0;
222 txerr_acc += txerr; txerr = 0;
223 rcvd_acc += rcvd; rcvd = 0;
224 rxerr_acc += rxerr; rxerr = 0;
225 rxcrc_acc += rxcrc; rxcrc = 0;
228 if(sent_acc >=10000) {
229 printf("\nOverall\tSENT %d\tTXERR %d\t",sent_acc,txerr_acc);
230 printf("RX %d\tERR %d\tCRC %d\tMISSED %d\n\n",rcvd_acc, rxerr_acc, rxcrc_acc, sent_acc-rcvd_acc);
238 int pending = pic_regs->pending;
239 if (pending & PIC_TIMER_INT){
240 hal_set_timeout(timer_delta);
243 if (EXPECTING_PKT()){
250 if (status & BPS_IDLE(SERDES_TX_BUF))
251 bp_send_from_buf(SERDES_TX_BUF, PORT_SERDES, 1, 0, NLINES_PER_PKT);
258 bp_send_from_buf(SERDES_TX_BUF, PORT_SERDES, 1, 0, NLINES_PER_PKT);
263 pic_regs->pending = PIC_TIMER_INT; // clear pending interrupt