2 * Copyright 2007,2008,2009 Free Software Foundation, Inc.
4 * This program is free software: you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation, either version 3 of the License, or
7 * (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
14 * You should have received a copy of the GNU General Public License
15 * along with this program. If not, see <http://www.gnu.org/licenses/>.
19 * This is a down and dirty test program that confirms that the we can
20 * coherently transmit different signals to two USRP2s connected via a
21 * mimo cable. This code runs in the USRP2 NOT connected to the
22 * ethernet. The USRP connected to the ethernet runs mimo_tx. The
23 * host runs test_mimo_tx.
31 #include "memory_map.h"
34 #include "buffer_pool.h"
39 #include "usrp2_eth_packet.h"
41 #include "app_common_v2.h"
42 #include "memcpy_wa.h"
49 #define FW_SETS_SEQNO 1 // define to 0 or 1 (FIXME must be 1 for now)
52 static int fw_seqno; // used when f/w is filling in sequence numbers
57 * Full duplex Tx and Rx between serdes and DSP pipelines
59 * Buffer 1 is used by the cpu to send frames to the host.
60 * Buffers 2 and 3 are used to double-buffer the DSP Rx to serdes flow
61 * Buffers 4 and 5 are used to double-buffer the serdes to DSP Tx flow
63 //#define CPU_RX_BUF 0 // eth -> cpu
65 #define DSP_RX_BUF_0 2 // dsp rx -> serdes (double buffer)
66 #define DSP_RX_BUF_1 3 // dsp rx -> serdes
67 #define DSP_TX_BUF_0 4 // serdes -> dsp tx (double buffer)
68 #define DSP_TX_BUF_1 5 // serdes -> dsp tx
71 * ==================================================================
72 * configure DSP TX double buffering state machine (serdes -> dsp)
73 * ==================================================================
76 // 4 lines of ethernet hdr + 1 line transport hdr + 2 lines (word0 + timestamp)
77 // DSP Tx reads word0 (flags) + timestamp followed by samples
79 #define DSP_TX_FIRST_LINE ((sizeof(u2_eth_hdr_t) + sizeof(u2_transport_hdr_t))/4)
81 // Receive from serdes
82 buf_cmd_args_t dsp_tx_recv_args = {
89 buf_cmd_args_t dsp_tx_send_args = {
91 DSP_TX_FIRST_LINE, // starts just past transport header
92 0 // filled in from last_line register
95 dbsm_t dsp_tx_sm; // the state machine
98 * =================================================================
99 * configure DSP RX double buffering state machine (dsp -> serdes)
100 * =================================================================
103 // 4 lines of ethernet hdr + 1 line transport hdr + 1 line (word0)
104 // DSP Rx writes timestamp followed by nlines_per_frame of samples
105 #define DSP_RX_FIRST_LINE ((sizeof(u2_eth_hdr_t) + sizeof(u2_transport_hdr_t))/4 + 1)
108 buf_cmd_args_t dsp_rx_recv_args = {
115 buf_cmd_args_t dsp_rx_send_args = {
117 0, // starts with ethernet header in line 0
118 0, // filled in from list_line register
121 dbsm_t dsp_rx_sm; // the state machine
124 // The mac address of the host we're sending to.
125 u2_mac_addr_t host_mac_addr;
128 // variables for streaming mode
130 static bool streaming_p = false;
131 static unsigned int streaming_items_per_frame = 0;
132 static int streaming_frame_count = 0;
133 #define FRAMES_PER_CMD 1000
135 bool is_streaming(void){ return streaming_p; }
137 // ----------------------------------------------------------------
141 restart_streaming(void)
144 dsp_rx_regs->clear_state = 1; // reset
147 streaming_frame_count = FRAMES_PER_CMD;
149 dsp_rx_regs->rx_command =
150 MK_RX_CMD(FRAMES_PER_CMD * streaming_items_per_frame,
151 streaming_items_per_frame,
152 1, 1); // set "chain" bit
154 // kick off the state machine
155 dbsm_start(&dsp_rx_sm);
157 dsp_rx_regs->rx_time = 0; // enqueue first of two commands
159 // make sure this one and the rest have the "now" and "chain" bits set.
160 dsp_rx_regs->rx_command =
161 MK_RX_CMD(FRAMES_PER_CMD * streaming_items_per_frame,
162 streaming_items_per_frame,
165 dsp_rx_regs->rx_time = 0; // enqueue second command
169 start_rx_streaming_cmd(const u2_mac_addr_t *host, op_start_rx_streaming_t *p)
171 host_mac_addr = *host; // remember who we're sending to
174 * Construct ethernet header and word0 and preload into two buffers
177 memset(&pkt, 0, sizeof(pkt));
178 pkt.ehdr.dst = *host;
179 pkt.ehdr.ethertype = U2_ETHERTYPE;
180 u2p_set_word0(&pkt.fixed, 0, 0);
181 // DSP RX will fill in timestamp
183 memcpy_wa(buffer_ram(DSP_RX_BUF_0), &pkt, sizeof(pkt));
184 memcpy_wa(buffer_ram(DSP_RX_BUF_1), &pkt, sizeof(pkt));
190 streaming_items_per_frame = p->items_per_frame;
199 dsp_rx_regs->clear_state = 1; // flush cmd queue
200 bp_clear_buf(DSP_RX_BUF_0);
201 bp_clear_buf(DSP_RX_BUF_1);
208 dsp_tx_regs->clear_state = 1;
209 bp_clear_buf(DSP_TX_BUF_0);
210 bp_clear_buf(DSP_TX_BUF_1);
213 int interp = 8; // * 4
215 // setup some defaults
217 dsp_tx_regs->freq = 429496730; // 10MHz
218 dsp_tx_regs->scale_iq = (tx_scale << 16) | tx_scale;
219 dsp_tx_regs->interp_rate = (1 << 9) | (1 << 8) | interp;
225 * Debugging ONLY. This will be handled by the tx_protocol_engine.
227 * This is called when the DSP Rx chain has filled in a packet.
228 * We set and increment the seqno, then return false, indicating
229 * that we didn't handle the packet. A bit of a kludge
230 * but it should work.
233 fw_sets_seqno_inspector(dbsm_t *sm, int buf_this) // returns false
235 uint32_t *p = buffer_ram(buf_this);
236 uint32_t seqno = fw_seqno++;
238 // KLUDGE all kinds of nasty magic numbers and embedded knowledge
240 t = (t & 0xffff00ff) | ((seqno & 0xff) << 8);
243 // queue up another rx command when required
244 if (streaming_p && --streaming_frame_count == 0){
245 streaming_frame_count = FRAMES_PER_CMD;
246 dsp_rx_regs->rx_time = 0;
249 return false; // we didn't handle the packet
255 buffer_irq_handler(unsigned irq)
257 // hal_toggle_leds(LED_A);
259 uint32_t status = buffer_pool_status->status;
261 if (0 && (status & ~BPS_IDLE_ALL)){
266 dbsm_process_status(&dsp_tx_sm, status);
267 dbsm_process_status(&dsp_rx_sm, status);
275 output_regs->led_src = 0x3; // h/w controls bottom two bits
276 clocks_enable_test_clk(true, 1);
278 putstr("\nMIMO Tx Slave\n");
280 cpu_tx_buf_dest_port = PORT_SERDES;
282 // ethernet_register_link_changed_callback(link_changed_callback);
285 clocks_mimo_config(MC_WE_LOCK_TO_MIMO);
287 // puts("post clocks_mimo_config");
290 // make bit 15 of Tx gpio's be a s/w output
291 hal_gpio_set_sel(GPIO_TX_BANK, 15, 's');
292 hal_gpio_set_ddr(GPIO_TX_BANK, 0x8000, 0x8000);
296 output_regs->debug_mux_ctrl = 1;
297 hal_gpio_set_sels(GPIO_TX_BANK, "0000000000000000");
298 hal_gpio_set_sels(GPIO_RX_BANK, "0000000000000000");
299 hal_gpio_set_ddr(GPIO_TX_BANK, 0xffff, 0xffff);
300 hal_gpio_set_ddr(GPIO_RX_BANK, 0xffff, 0xffff);
304 // initialize double buffering state machine for ethernet -> DSP Tx
306 dbsm_init(&dsp_tx_sm, DSP_TX_BUF_0,
307 &dsp_tx_recv_args, &dsp_tx_send_args,
311 //output_regs->flush_icache = 1;
313 // initialize double buffering state machine for DSP RX -> Ethernet
316 dbsm_init(&dsp_rx_sm, DSP_RX_BUF_0,
317 &dsp_rx_recv_args, &dsp_rx_send_args,
318 fw_sets_seqno_inspector);
321 dbsm_init(&dsp_rx_sm, DSP_RX_BUF_0,
322 &dsp_rx_recv_args, &dsp_rx_send_args,
326 // puts("post dbsm_init's");
328 // tell app_common that this dbsm could be sending to the ethernet
329 ac_could_be_sending_to_eth = &dsp_rx_sm;
332 // program tx registers
335 // puts("post setup_tx");
337 // kick off the state machine
338 dbsm_start(&dsp_tx_sm);
340 // puts("post dbsm_start");
345 // hal_gpio_write(GPIO_TX_BANK, which, 0x8000);
348 buffer_irq_handler(0);
350 int pending = pic_regs->pending; // poll for under or overrun
352 if (pending & PIC_UNDERRUN_INT){
353 dbsm_handle_tx_underrun(&dsp_tx_sm);
354 pic_regs->pending = PIC_UNDERRUN_INT; // clear interrupt
358 if (pending & PIC_OVERRUN_INT){
359 dbsm_handle_rx_overrun(&dsp_rx_sm);
360 pic_regs->pending = PIC_OVERRUN_INT; // clear pending interrupt
362 // FIXME Figure out how to handle this robustly.
363 // Any buffers that are emptying should be allowed to drain...
366 // restart_streaming();
367 // FIXME report error
370 // FIXME report error