2 * Copyright 2007,2008,2009 Free Software Foundation, Inc.
4 * This program is free software: you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation, either version 3 of the License, or
7 * (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
14 * You should have received a copy of the GNU General Public License
15 * along with this program. If not, see <http://www.gnu.org/licenses/>.
19 * This is a down and dirty test program that confirms that the we can
20 * coherently transmit different signals to two USRP2s connected via a
21 * mimo cable. This code runs in the USRP2 connected to the ethernet.
22 * The other USRP runs mimo_tx_slave. The host runs test_mimo_tx.
30 #include "memory_map.h"
33 #include "buffer_pool.h"
38 #include "usrp2_eth_packet.h"
40 #include "mimo_app_common_v2.h"
41 #include "memcpy_wa.h"
47 #define FW_SETS_SEQNO 1 // define to 0 or 1 (FIXME must be 1 for now)
50 static int fw_seqno; // used when f/w is filling in sequence numbers
55 * Experimental code to transmit packets to DSP Tx and SERDES
57 * Hard wire the Tx config so we don't have to deal with control stuff yet.
64 //#define CPU_TX_BUF 7 // cpu -> eth
66 // 4 lines of ethernet hdr + 1 line transport hdr + 2 lines (word0 + timestamp)
67 // DSP Tx reads word0 (flags) + timestamp followed by samples
69 #define DSP_TX_FIRST_LINE ((sizeof(u2_eth_hdr_t) + sizeof(u2_transport_hdr_t))/4)
71 // Receive from ethernet
72 buf_cmd_args_t bsm12_recv_args = {
79 buf_cmd_args_t bsm12_send0_args = {
81 DSP_TX_FIRST_LINE, // starts just past transport header
82 0 // filled in from last_line register
86 buf_cmd_args_t bsm12_send1_args = {
88 0, // starts just past transport header
89 0 // filled in from last_line register
92 bsm12_t bsm12_sm; // the state machine
96 * ================================================================
97 * configure DSP RX double buffering state machine (dsp -> eth)
98 * ================================================================
101 // 4 lines of ethernet hdr + 1 line transport hdr + 1 line (word0)
102 // DSP Rx writes timestamp followed by nlines_per_frame of samples
103 #define DSP_RX_FIRST_LINE ((sizeof(u2_eth_hdr_t) + sizeof(u2_transport_hdr_t))/4 + 1)
106 buf_cmd_args_t dsp_rx_recv_args = {
113 buf_cmd_args_t dsp_rx_send_args = {
115 0, // starts with ethernet header in line 0
116 0, // filled in from list_line register
119 dbsm_t dsp_rx_sm; // the state machine
123 // The mac address of the host we're sending to.
124 u2_mac_addr_t host_mac_addr;
127 // variables for streaming mode
129 static bool streaming_p = false;
130 static unsigned int streaming_items_per_frame = 0;
131 static int streaming_frame_count = 0;
132 #define FRAMES_PER_CMD 1000
134 bool is_streaming(void){ return streaming_p; }
137 // ----------------------------------------------------------------
141 restart_streaming(void)
145 dsp_rx_regs->clear_state = 1; // reset
148 streaming_frame_count = FRAMES_PER_CMD;
150 dsp_rx_regs->rx_command =
151 MK_RX_CMD(FRAMES_PER_CMD * streaming_items_per_frame,
152 streaming_items_per_frame,
153 1, 1); // set "chain" bit
155 // kick off the state machine
156 dbsm_start(&dsp_rx_sm);
158 dsp_rx_regs->rx_time = 0; // enqueue first of two commands
160 // make sure this one and the rest have the "now" and "chain" bits set.
161 dsp_rx_regs->rx_command =
162 MK_RX_CMD(FRAMES_PER_CMD * streaming_items_per_frame,
163 streaming_items_per_frame,
166 dsp_rx_regs->rx_time = 0; // enqueue second command
171 start_rx_streaming_cmd(const u2_mac_addr_t *host, op_start_rx_streaming_t *p)
174 host_mac_addr = *host; // remember who we're sending to
177 * Construct ethernet header and word0 and preload into two buffers
180 memset(&pkt, 0, sizeof(pkt));
181 pkt.ehdr.dst = *host;
182 pkt.ehdr.ethertype = U2_ETHERTYPE;
183 u2p_set_word0(&pkt.fixed, 0, 0);
184 // DSP RX will fill in timestamp
186 memcpy_wa(buffer_ram(DSP_RX_BUF_0), &pkt, sizeof(pkt));
187 memcpy_wa(buffer_ram(DSP_RX_BUF_1), &pkt, sizeof(pkt));
193 streaming_items_per_frame = p->items_per_frame;
204 dsp_rx_regs->clear_state = 1; // flush cmd queue
205 bp_clear_buf(DSP_RX_BUF_0);
206 bp_clear_buf(DSP_RX_BUF_1);
214 dsp_tx_regs->clear_state = 1;
217 int interp = 8; // * 4
219 // setup some defaults
221 dsp_tx_regs->freq = 429496730; // 10MHz
222 dsp_tx_regs->scale_iq = (tx_scale << 16) | tx_scale;
223 dsp_tx_regs->interp_rate = (1 << 9) | (1 << 8) | interp;
230 * Debugging ONLY. This will be handled by the tx_protocol_engine.
232 * This is called when the DSP Rx chain has filled in a packet.
233 * We set and increment the seqno, then return false, indicating
234 * that we didn't handle the packet. A bit of a kludge
235 * but it should work.
238 fw_sets_seqno_inspector(bsm12_t *sm, int buf_this)
240 uint32_t *p = buffer_ram(buf_this);
241 uint32_t seqno = fw_seqno++;
243 // KLUDGE all kinds of nasty magic numbers and embedded knowledge
245 t = (t & 0xffff00ff) | ((seqno & 0xff) << 8);
248 // queue up another rx command when required
249 if (streaming_p && --streaming_frame_count == 0){
250 streaming_frame_count = FRAMES_PER_CMD;
251 dsp_rx_regs->rx_time = 0;
254 return false; // we didn't handle the packet
261 buffer_irq_handler(unsigned irq)
263 uint32_t status = buffer_pool_status->status;
265 bsm12_process_status(&bsm12_sm, status);
273 putstr("\nMIMO Tx\n");
274 print_mac_addr(ethernet_mac_addr()->addr);
277 ethernet_register_link_changed_callback(link_changed_callback);
280 clocks_mimo_config(MC_WE_DONT_LOCK | MC_PROVIDE_CLK_TO_MIMO);
283 // make bit 15 of Tx gpio's be a s/w output
284 hal_gpio_set_sel(GPIO_TX_BANK, 15, 's');
285 hal_gpio_set_ddr(GPIO_TX_BANK, 0x8000, 0x8000);
288 output_regs->debug_mux_ctrl = 1;
290 hal_gpio_set_sels(GPIO_TX_BANK, "1111111111111111");
291 hal_gpio_set_sels(GPIO_RX_BANK, "1111111111111111");
292 hal_gpio_set_ddr(GPIO_TX_BANK, 0xffff, 0xffff);
293 hal_gpio_set_ddr(GPIO_RX_BANK, 0xffff, 0xffff);
297 // initialize double buffering state machine for ethernet -> DSP Tx
299 bsm12_init(&bsm12_sm, BUF_BSM12_0,
300 &bsm12_recv_args, &bsm12_send0_args, &bsm12_send1_args,
305 // initialize double buffering state machine for DSP RX -> Ethernet
308 dbsm_init(&dsp_rx_sm, DSP_RX_BUF_0,
309 &dsp_rx_recv_args, &dsp_rx_send_args,
310 fw_sets_seqno_inspector);
313 dbsm_init(&dsp_rx_sm, DSP_RX_BUF_0,
314 &dsp_rx_recv_args, &dsp_rx_send_args,
318 // tell app_common that this dbsm could be sending to the ethernet
319 ac_could_be_sending_to_eth = &dsp_rx_sm;
323 // program tx registers
326 // kick off the state machine
327 bsm12_start(&bsm12_sm);
332 // hal_gpio_write(GPIO_TX_BANK, which, 0x8000);
335 buffer_irq_handler(0);
337 int pending = pic_regs->pending; // poll for under or overrun
339 if (pending & PIC_UNDERRUN_INT){
340 // dbsm_handle_tx_underrun(&dsp_tx_sm);
341 pic_regs->pending = PIC_UNDERRUN_INT; // clear interrupt
345 if (pending & PIC_OVERRUN_INT){
346 // dbsm_handle_rx_overrun(&dsp_rx_sm);
347 pic_regs->pending = PIC_OVERRUN_INT; // clear pending interrupt
349 // FIXME Figure out how to handle this robustly.
350 // Any buffers that are emptying should be allowed to drain...
353 // restart_streaming();
354 // FIXME report error
357 // FIXME report error