2 * Copyright 2007,2008 Free Software Foundation, Inc.
4 * This program is free software: you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation, either version 3 of the License, or
7 * (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
14 * You should have received a copy of the GNU General Public License
15 * along with this program. If not, see <http://www.gnu.org/licenses/>.
23 #include "memory_map.h"
26 #include "buffer_pool.h"
31 #include "usrp2_eth_packet.h"
33 #include "app_common_v2.h"
34 #include "memcpy_wa.h"
39 #include <usrp2_i2c_addr.h>
43 #define FW_SETS_SEQNO 1 // define to 0 or 1 (FIXME must be 1 for now)
46 static int fw_seqno; // used when f/w is filling in sequence numbers
51 * Full duplex Tx and Rx between ethernet and DSP pipelines
53 * Buffer 1 is used by the cpu to send frames to the host.
54 * Buffers 2 and 3 are used to double-buffer the DSP Rx to eth flow
55 * Buffers 4 and 5 are used to double-buffer the eth to DSP Tx eth flow
57 //#define CPU_RX_BUF 0 // eth -> cpu
59 #define DSP_RX_BUF_0 2 // dsp rx -> eth (double buffer)
60 #define DSP_RX_BUF_1 3 // dsp rx -> eth
61 #define DSP_TX_BUF_0 4 // eth -> dsp tx (double buffer)
62 #define DSP_TX_BUF_1 5 // eth -> dsp tx
65 * ================================================================
66 * configure DSP TX double buffering state machine (eth -> dsp)
67 * ================================================================
70 // 4 lines of ethernet hdr + 1 line transport hdr + 2 lines (word0 + timestamp)
71 // DSP Tx reads word0 (flags) + timestamp followed by samples
73 #define DSP_TX_FIRST_LINE ((sizeof(u2_eth_hdr_t) + sizeof(u2_transport_hdr_t))/4)
75 // Receive from ethernet
76 buf_cmd_args_t dsp_tx_recv_args = {
83 buf_cmd_args_t dsp_tx_send_args = {
85 DSP_TX_FIRST_LINE, // starts just past transport header
86 0 // filled in from last_line register
89 dbsm_t dsp_tx_sm; // the state machine
92 * ================================================================
93 * configure DSP RX double buffering state machine (dsp -> eth)
94 * ================================================================
97 // 4 lines of ethernet hdr + 1 line transport hdr + 1 line (word0)
98 // DSP Rx writes timestamp followed by nlines_per_frame of samples
99 #define DSP_RX_FIRST_LINE ((sizeof(u2_eth_hdr_t) + sizeof(u2_transport_hdr_t))/4 + 1)
102 buf_cmd_args_t dsp_rx_recv_args = {
109 buf_cmd_args_t dsp_rx_send_args = {
111 0, // starts with ethernet header in line 0
112 0, // filled in from list_line register
115 dbsm_t dsp_rx_sm; // the state machine
118 // The mac address of the host we're sending to.
119 u2_mac_addr_t host_mac_addr;
122 // variables for streaming mode
124 static bool streaming_p = false;
125 static unsigned int streaming_items_per_frame = 0;
126 static int streaming_frame_count = 0;
127 #define FRAMES_PER_CMD 1000
129 bool is_streaming(void){ return streaming_p; }
131 // ----------------------------------------------------------------
135 restart_streaming(void)
138 dsp_rx_regs->clear_state = 1; // reset
141 streaming_frame_count = FRAMES_PER_CMD;
143 dsp_rx_regs->rx_command =
144 MK_RX_CMD(FRAMES_PER_CMD * streaming_items_per_frame,
145 streaming_items_per_frame,
146 1, 1); // set "chain" bit
148 // kick off the state machine
149 dbsm_start(&dsp_rx_sm);
151 dsp_rx_regs->rx_time = 0; // enqueue first of two commands
153 // make sure this one and the rest have the "now" and "chain" bits set.
154 dsp_rx_regs->rx_command =
155 MK_RX_CMD(FRAMES_PER_CMD * streaming_items_per_frame,
156 streaming_items_per_frame,
159 dsp_rx_regs->rx_time = 0; // enqueue second command
163 start_rx_streaming_cmd(const u2_mac_addr_t *host, op_start_rx_streaming_t *p)
165 host_mac_addr = *host; // remember who we're sending to
168 * Construct ethernet header and word0 and preload into two buffers
171 memset(&pkt, 0, sizeof(pkt));
172 pkt.ehdr.dst = *host;
173 pkt.ehdr.ethertype = U2_ETHERTYPE;
174 u2p_set_word0(&pkt.fixed, 0, 0);
175 // DSP RX will fill in timestamp
177 memcpy_wa(buffer_ram(DSP_RX_BUF_0), &pkt, sizeof(pkt));
178 memcpy_wa(buffer_ram(DSP_RX_BUF_1), &pkt, sizeof(pkt));
184 streaming_items_per_frame = p->items_per_frame;
193 dsp_rx_regs->clear_state = 1; // flush cmd queue
194 bp_clear_buf(DSP_RX_BUF_0);
195 bp_clear_buf(DSP_RX_BUF_1);
202 dsp_tx_regs->clear_state = 1;
203 bp_clear_buf(DSP_TX_BUF_0);
204 bp_clear_buf(DSP_TX_BUF_1);
209 // setup some defaults
211 dsp_tx_regs->freq = 0;
212 dsp_tx_regs->scale_iq = (tx_scale << 16) | tx_scale;
213 dsp_tx_regs->interp_rate = interp;
219 * Debugging ONLY. This will be handled by the tx_protocol_engine.
221 * This is called when the DSP Rx chain has filled in a packet.
222 * We set and increment the seqno, then return false, indicating
223 * that we didn't handle the packet. A bit of a kludge
224 * but it should work.
227 fw_sets_seqno_inspector(dbsm_t *sm, int buf_this) // returns false
229 uint32_t *p = buffer_ram(buf_this);
230 uint32_t seqno = fw_seqno++;
232 // KLUDGE all kinds of nasty magic numbers and embedded knowledge
234 t = (t & 0xffff00ff) | ((seqno & 0xff) << 8);
237 // queue up another rx command when required
238 if (streaming_p && --streaming_frame_count == 0){
239 streaming_frame_count = FRAMES_PER_CMD;
240 dsp_rx_regs->rx_time = 0;
243 return false; // we didn't handle the packet
249 buffer_irq_handler(unsigned irq)
251 uint32_t status = buffer_pool_status->status;
253 dbsm_process_status(&dsp_tx_sm, status);
254 dbsm_process_status(&dsp_rx_sm, status);
260 output_regs->ram_page = 1<<10;
262 extram[0] = 0xDEADBEEF;
263 extram[1] = 0xF00D1234;
264 extram[7] = 0x76543210;
266 output_regs->ram_page = 2<<10;
267 extram[7] = 0x55555555;
268 extram[1] = 0xaaaaaaaa;
269 extram[0] = 0xeeeeeeee;
271 output_regs->ram_page = 1<<10;
277 if((i != 0xDEADBEEF)||(j!=0x76543210)||(k!=0xF00D1234)) {
278 puts("RAM FAIL1!\n");
285 output_regs->ram_page = 2<<10;
291 if((i != 0xeeeeeeee)||(j!=0x55555555)||(k!=0xaaaaaaaa)) {
292 puts("RAM FAIL2!\n");
305 puts("FAILED INIT of Card\n");
309 unsigned char buf[512];
310 i = sd_read_block(2048,buf);
312 puts("READ Command Rejected\n");
315 if((buf[0]==0xb8)&&(buf[1]==0x08)&&(buf[2]==0x00)&&(buf[3]==0x50))
318 puts("Read bad data from SD Card\n");
329 putstr("\nFactory Test\n");
331 print_mac_addr(ethernet_mac_addr()->addr);
349 print_mac_addr(ethernet_mac_addr()->addr);
352 output_regs->led_src = 0x7; // make bottom 3 controlled by HW
354 ethernet_register_link_changed_callback(link_changed_callback);
357 clocks_enable_tx_dboard(true,1);
358 clocks_mimo_config(MC_WE_LOCK_TO_SMA);
360 // make bit 15 of Tx gpio's be a s/w output
361 hal_gpio_set_sel(GPIO_TX_BANK, 15, 's');
362 hal_gpio_set_ddr(GPIO_TX_BANK, 0x8000, 0x8000);
365 output_regs->debug_mux_ctrl = 1;
367 hal_gpio_set_sels(GPIO_TX_BANK, "1111111111111111");
368 hal_gpio_set_sels(GPIO_RX_BANK, "1111111111111111");
369 hal_gpio_set_ddr(GPIO_TX_BANK, 0xffff, 0xffff);
370 hal_gpio_set_ddr(GPIO_RX_BANK, 0xffff, 0xffff);
374 // initialize double buffering state machine for ethernet -> DSP Tx
376 dbsm_init(&dsp_tx_sm, DSP_TX_BUF_0,
377 &dsp_tx_recv_args, &dsp_tx_send_args,
381 // initialize double buffering state machine for DSP RX -> Ethernet
384 dbsm_init(&dsp_rx_sm, DSP_RX_BUF_0,
385 &dsp_rx_recv_args, &dsp_rx_send_args,
386 fw_sets_seqno_inspector);
389 dbsm_init(&dsp_rx_sm, DSP_RX_BUF_0,
390 &dsp_rx_recv_args, &dsp_rx_send_args,
394 // tell app_common that this dbsm could be sending to the ethernet
395 ac_could_be_sending_to_eth = &dsp_rx_sm;
398 // program tx registers
401 // kick off the state machine
402 dbsm_start(&dsp_tx_sm);
407 // hal_gpio_write(GPIO_TX_BANK, which, 0x8000);
410 buffer_irq_handler(0);
412 int pending = pic_regs->pending; // poll for under or overrun
414 if (pending & PIC_UNDERRUN_INT){
415 dbsm_handle_tx_underrun(&dsp_tx_sm);
416 pic_regs->pending = PIC_UNDERRUN_INT; // clear interrupt
420 if (pending & PIC_OVERRUN_INT){
421 dbsm_handle_rx_overrun(&dsp_rx_sm);
422 pic_regs->pending = PIC_OVERRUN_INT; // clear pending interrupt
424 // FIXME Figure out how to handle this robustly.
425 // Any buffers that are emptying should be allowed to drain...
428 // restart_streaming();
429 // FIXME report error
432 // FIXME report error