2 * Copyright 2007,2008 Free Software Foundation, Inc.
4 * This program is free software: you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation, either version 3 of the License, or
7 * (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
14 * You should have received a copy of the GNU General Public License
15 * along with this program. If not, see <http://www.gnu.org/licenses/>.
23 #include "memory_map.h"
26 #include "buffer_pool.h"
31 #include "usrp2_eth_packet.h"
33 #include "app_common_v2.h"
34 #include "memcpy_wa.h"
39 #include <usrp2_i2c_addr.h>
42 #define HW_REV_MAJOR 3
43 #define HW_REV_MINOR 0
45 #define FW_SETS_SEQNO 1 // define to 0 or 1 (FIXME must be 1 for now)
48 static int fw_seqno; // used when f/w is filling in sequence numbers
53 * Full duplex Tx and Rx between ethernet and DSP pipelines
55 * Buffer 1 is used by the cpu to send frames to the host.
56 * Buffers 2 and 3 are used to double-buffer the DSP Rx to eth flow
57 * Buffers 4 and 5 are used to double-buffer the eth to DSP Tx eth flow
59 //#define CPU_RX_BUF 0 // eth -> cpu
61 #define DSP_RX_BUF_0 2 // dsp rx -> eth (double buffer)
62 #define DSP_RX_BUF_1 3 // dsp rx -> eth
63 #define DSP_TX_BUF_0 4 // eth -> dsp tx (double buffer)
64 #define DSP_TX_BUF_1 5 // eth -> dsp tx
67 * ================================================================
68 * configure DSP TX double buffering state machine (eth -> dsp)
69 * ================================================================
72 // 4 lines of ethernet hdr + 1 line transport hdr + 2 lines (word0 + timestamp)
73 // DSP Tx reads word0 (flags) + timestamp followed by samples
75 #define DSP_TX_FIRST_LINE ((sizeof(u2_eth_hdr_t) + sizeof(u2_transport_hdr_t))/4)
77 // Receive from ethernet
78 buf_cmd_args_t dsp_tx_recv_args = {
85 buf_cmd_args_t dsp_tx_send_args = {
87 DSP_TX_FIRST_LINE, // starts just past transport header
88 0 // filled in from last_line register
91 dbsm_t dsp_tx_sm; // the state machine
94 * ================================================================
95 * configure DSP RX double buffering state machine (dsp -> eth)
96 * ================================================================
99 // 4 lines of ethernet hdr + 1 line transport hdr + 1 line (word0)
100 // DSP Rx writes timestamp followed by nlines_per_frame of samples
101 #define DSP_RX_FIRST_LINE ((sizeof(u2_eth_hdr_t) + sizeof(u2_transport_hdr_t))/4 + 1)
104 buf_cmd_args_t dsp_rx_recv_args = {
111 buf_cmd_args_t dsp_rx_send_args = {
113 0, // starts with ethernet header in line 0
114 0, // filled in from list_line register
117 dbsm_t dsp_rx_sm; // the state machine
120 // The mac address of the host we're sending to.
121 u2_mac_addr_t host_mac_addr;
124 // variables for streaming mode
126 static bool streaming_p = false;
127 static unsigned int streaming_items_per_frame = 0;
128 static int streaming_frame_count = 0;
129 #define FRAMES_PER_CMD 1000
131 bool is_streaming(void){ return streaming_p; }
133 // ----------------------------------------------------------------
137 restart_streaming(void)
140 dsp_rx_regs->clear_state = 1; // reset
143 streaming_frame_count = FRAMES_PER_CMD;
145 dsp_rx_regs->rx_command =
146 MK_RX_CMD(FRAMES_PER_CMD * streaming_items_per_frame,
147 streaming_items_per_frame,
148 1, 1); // set "chain" bit
150 // kick off the state machine
151 dbsm_start(&dsp_rx_sm);
153 dsp_rx_regs->rx_time = 0; // enqueue first of two commands
155 // make sure this one and the rest have the "now" and "chain" bits set.
156 dsp_rx_regs->rx_command =
157 MK_RX_CMD(FRAMES_PER_CMD * streaming_items_per_frame,
158 streaming_items_per_frame,
161 dsp_rx_regs->rx_time = 0; // enqueue second command
165 start_rx_streaming_cmd(const u2_mac_addr_t *host, op_start_rx_streaming_t *p)
167 host_mac_addr = *host; // remember who we're sending to
170 * Construct ethernet header and word0 and preload into two buffers
173 memset(&pkt, 0, sizeof(pkt));
174 pkt.ehdr.dst = *host;
175 pkt.ehdr.ethertype = U2_ETHERTYPE;
176 u2p_set_word0(&pkt.fixed, 0, 0);
177 // DSP RX will fill in timestamp
179 memcpy_wa(buffer_ram(DSP_RX_BUF_0), &pkt, sizeof(pkt));
180 memcpy_wa(buffer_ram(DSP_RX_BUF_1), &pkt, sizeof(pkt));
186 streaming_items_per_frame = p->items_per_frame;
195 dsp_rx_regs->clear_state = 1; // flush cmd queue
196 bp_clear_buf(DSP_RX_BUF_0);
197 bp_clear_buf(DSP_RX_BUF_1);
204 dsp_tx_regs->clear_state = 1;
205 bp_clear_buf(DSP_TX_BUF_0);
206 bp_clear_buf(DSP_TX_BUF_1);
211 // setup some defaults
213 dsp_tx_regs->freq = 0;
214 dsp_tx_regs->scale_iq = (tx_scale << 16) | tx_scale;
215 dsp_tx_regs->interp_rate = interp;
221 * Debugging ONLY. This will be handled by the tx_protocol_engine.
223 * This is called when the DSP Rx chain has filled in a packet.
224 * We set and increment the seqno, then return false, indicating
225 * that we didn't handle the packet. A bit of a kludge
226 * but it should work.
229 fw_sets_seqno_inspector(dbsm_t *sm, int buf_this) // returns false
231 uint32_t *p = buffer_ram(buf_this);
232 uint32_t seqno = fw_seqno++;
234 // KLUDGE all kinds of nasty magic numbers and embedded knowledge
236 t = (t & 0xffff00ff) | ((seqno & 0xff) << 8);
239 // queue up another rx command when required
240 if (streaming_p && --streaming_frame_count == 0){
241 streaming_frame_count = FRAMES_PER_CMD;
242 dsp_rx_regs->rx_time = 0;
245 return false; // we didn't handle the packet
251 buffer_irq_handler(unsigned irq)
253 uint32_t status = buffer_pool_status->status;
255 dbsm_process_status(&dsp_tx_sm, status);
256 dbsm_process_status(&dsp_rx_sm, status);
264 putstr("\nset_hw_rev\n");
267 unsigned char maj = HW_REV_MAJOR;
268 unsigned char min = HW_REV_MINOR;
269 ok = eeprom_write(I2C_ADDR_MBOARD, MBOARD_REV_MSB, &maj, 1);
270 ok &= eeprom_write(I2C_ADDR_MBOARD, MBOARD_REV_LSB, &min, 1);
273 printf("OK: set h/w rev to %d.%d\n", HW_REV_MAJOR, HW_REV_MINOR);
275 printf("FAILED to set h/w rev to %d.%d\n", HW_REV_MAJOR, HW_REV_MINOR);
277 putstr("\nFactory Test TXRX\n");
278 print_mac_addr(ethernet_mac_addr()->addr);
281 output_regs->led_src = 0x7; // make bottom 3 controlled by HW
283 ethernet_register_link_changed_callback(link_changed_callback);
286 clocks_enable_tx_dboard(true,1);
287 clocks_mimo_config(MC_WE_LOCK_TO_SMA);
289 // make bit 15 of Tx gpio's be a s/w output
290 hal_gpio_set_sel(GPIO_TX_BANK, 15, 's');
291 hal_gpio_set_ddr(GPIO_TX_BANK, 0x8000, 0x8000);
294 output_regs->debug_mux_ctrl = 1;
296 hal_gpio_set_sels(GPIO_TX_BANK, "1111111111111111");
297 hal_gpio_set_sels(GPIO_RX_BANK, "1111111111111111");
298 hal_gpio_set_ddr(GPIO_TX_BANK, 0xffff, 0xffff);
299 hal_gpio_set_ddr(GPIO_RX_BANK, 0xffff, 0xffff);
303 // initialize double buffering state machine for ethernet -> DSP Tx
305 dbsm_init(&dsp_tx_sm, DSP_TX_BUF_0,
306 &dsp_tx_recv_args, &dsp_tx_send_args,
310 // initialize double buffering state machine for DSP RX -> Ethernet
313 dbsm_init(&dsp_rx_sm, DSP_RX_BUF_0,
314 &dsp_rx_recv_args, &dsp_rx_send_args,
315 fw_sets_seqno_inspector);
318 dbsm_init(&dsp_rx_sm, DSP_RX_BUF_0,
319 &dsp_rx_recv_args, &dsp_rx_send_args,
323 // tell app_common that this dbsm could be sending to the ethernet
324 ac_could_be_sending_to_eth = &dsp_rx_sm;
327 // program tx registers
330 // kick off the state machine
331 dbsm_start(&dsp_tx_sm);
336 // hal_gpio_write(GPIO_TX_BANK, which, 0x8000);
339 buffer_irq_handler(0);
341 int pending = pic_regs->pending; // poll for under or overrun
343 if (pending & PIC_UNDERRUN_INT){
344 dbsm_handle_tx_underrun(&dsp_tx_sm);
345 pic_regs->pending = PIC_UNDERRUN_INT; // clear interrupt
349 if (pending & PIC_OVERRUN_INT){
350 dbsm_handle_rx_overrun(&dsp_rx_sm);
351 pic_regs->pending = PIC_OVERRUN_INT; // clear pending interrupt
353 // FIXME Figure out how to handle this robustly.
354 // Any buffers that are emptying should be allowed to drain...
357 // restart_streaming();
358 // FIXME report error
361 // FIXME report error