2 * Copyright 2007,2008 Free Software Foundation, Inc.
4 * This program is free software: you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation, either version 3 of the License, or
7 * (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
14 * You should have received a copy of the GNU General Public License
15 * along with this program. If not, see <http://www.gnu.org/licenses/>.
23 #include "memory_map.h"
26 #include "buffer_pool.h"
31 #include "usrp2_eth_packet.h"
33 #include "app_common_v2.h"
34 #include "memcpy_wa.h"
39 #include <usrp2_i2c_addr.h>
41 #define HW_REV_MAJOR 3
42 #define HW_REV_MINOR 0
44 #define FW_SETS_SEQNO 1 // define to 0 or 1 (FIXME must be 1 for now)
47 static int fw_seqno; // used when f/w is filling in sequence numbers
52 * Full duplex Tx and Rx between ethernet and DSP pipelines
54 * Buffer 1 is used by the cpu to send frames to the host.
55 * Buffers 2 and 3 are used to double-buffer the DSP Rx to eth flow
56 * Buffers 4 and 5 are used to double-buffer the eth to DSP Tx eth flow
58 //#define CPU_RX_BUF 0 // eth -> cpu
60 #define DSP_RX_BUF_0 2 // dsp rx -> eth (double buffer)
61 #define DSP_RX_BUF_1 3 // dsp rx -> eth
62 #define DSP_TX_BUF_0 4 // eth -> dsp tx (double buffer)
63 #define DSP_TX_BUF_1 5 // eth -> dsp tx
66 * ================================================================
67 * configure DSP TX double buffering state machine (eth -> dsp)
68 * ================================================================
71 // 4 lines of ethernet hdr + 1 line transport hdr + 2 lines (word0 + timestamp)
72 // DSP Tx reads word0 (flags) + timestamp followed by samples
74 #define DSP_TX_FIRST_LINE ((sizeof(u2_eth_hdr_t) + sizeof(u2_transport_hdr_t))/4)
76 // Receive from ethernet
77 buf_cmd_args_t dsp_tx_recv_args = {
84 buf_cmd_args_t dsp_tx_send_args = {
86 DSP_TX_FIRST_LINE, // starts just past transport header
87 0 // filled in from last_line register
90 dbsm_t dsp_tx_sm; // the state machine
93 * ================================================================
94 * configure DSP RX double buffering state machine (dsp -> eth)
95 * ================================================================
98 // 4 lines of ethernet hdr + 1 line transport hdr + 1 line (word0)
99 // DSP Rx writes timestamp followed by nlines_per_frame of samples
100 #define DSP_RX_FIRST_LINE ((sizeof(u2_eth_hdr_t) + sizeof(u2_transport_hdr_t))/4 + 1)
103 buf_cmd_args_t dsp_rx_recv_args = {
110 buf_cmd_args_t dsp_rx_send_args = {
112 0, // starts with ethernet header in line 0
113 0, // filled in from list_line register
116 dbsm_t dsp_rx_sm; // the state machine
119 // The mac address of the host we're sending to.
120 u2_mac_addr_t host_mac_addr;
123 // variables for streaming mode
125 static bool streaming_p = false;
126 static unsigned int streaming_items_per_frame = 0;
127 static int streaming_frame_count = 0;
128 #define FRAMES_PER_CMD 1000
130 bool is_streaming(void){ return streaming_p; }
132 // ----------------------------------------------------------------
136 restart_streaming(void)
139 dsp_rx_regs->clear_state = 1; // reset
142 streaming_frame_count = FRAMES_PER_CMD;
144 dsp_rx_regs->rx_command =
145 MK_RX_CMD(FRAMES_PER_CMD * streaming_items_per_frame,
146 streaming_items_per_frame,
147 1, 1); // set "chain" bit
149 // kick off the state machine
150 dbsm_start(&dsp_rx_sm);
152 dsp_rx_regs->rx_time = 0; // enqueue first of two commands
154 // make sure this one and the rest have the "now" and "chain" bits set.
155 dsp_rx_regs->rx_command =
156 MK_RX_CMD(FRAMES_PER_CMD * streaming_items_per_frame,
157 streaming_items_per_frame,
160 dsp_rx_regs->rx_time = 0; // enqueue second command
164 start_rx_streaming_cmd(const u2_mac_addr_t *host, op_start_rx_streaming_t *p)
166 host_mac_addr = *host; // remember who we're sending to
169 * Construct ethernet header and word0 and preload into two buffers
172 memset(&pkt, 0, sizeof(pkt));
173 pkt.ehdr.dst = *host;
174 pkt.ehdr.ethertype = U2_ETHERTYPE;
175 u2p_set_word0(&pkt.fixed, 0, 0);
176 // DSP RX will fill in timestamp
178 memcpy_wa(buffer_ram(DSP_RX_BUF_0), &pkt, sizeof(pkt));
179 memcpy_wa(buffer_ram(DSP_RX_BUF_1), &pkt, sizeof(pkt));
185 streaming_items_per_frame = p->items_per_frame;
194 dsp_rx_regs->clear_state = 1; // flush cmd queue
195 bp_clear_buf(DSP_RX_BUF_0);
196 bp_clear_buf(DSP_RX_BUF_1);
203 dsp_tx_regs->clear_state = 1;
204 bp_clear_buf(DSP_TX_BUF_0);
205 bp_clear_buf(DSP_TX_BUF_1);
210 // setup some defaults
212 dsp_tx_regs->freq = 0;
213 dsp_tx_regs->scale_iq = (tx_scale << 16) | tx_scale;
214 dsp_tx_regs->interp_rate = interp;
220 * Debugging ONLY. This will be handled by the tx_protocol_engine.
222 * This is called when the DSP Rx chain has filled in a packet.
223 * We set and increment the seqno, then return false, indicating
224 * that we didn't handle the packet. A bit of a kludge
225 * but it should work.
228 fw_sets_seqno_inspector(dbsm_t *sm, int buf_this) // returns false
230 uint32_t *p = buffer_ram(buf_this);
231 uint32_t seqno = fw_seqno++;
233 // KLUDGE all kinds of nasty magic numbers and embedded knowledge
235 t = (t & 0xffff00ff) | ((seqno & 0xff) << 8);
238 // queue up another rx command when required
239 if (streaming_p && --streaming_frame_count == 0){
240 streaming_frame_count = FRAMES_PER_CMD;
241 dsp_rx_regs->rx_time = 0;
244 return false; // we didn't handle the packet
250 buffer_irq_handler(unsigned irq)
252 uint32_t status = buffer_pool_status->status;
254 dbsm_process_status(&dsp_tx_sm, status);
255 dbsm_process_status(&dsp_rx_sm, status);
263 putstr("\nset_hw_rev\n");
266 unsigned char maj = HW_REV_MAJOR;
267 unsigned char min = HW_REV_MINOR;
268 ok = eeprom_write(I2C_ADDR_MBOARD, MBOARD_REV_MSB, &maj, 1);
269 ok &= eeprom_write(I2C_ADDR_MBOARD, MBOARD_REV_LSB, &min, 1);
272 printf("OK: set h/w rev to %d.%d\n", HW_REV_MAJOR, HW_REV_MINOR);
274 printf("FAILED to set h/w rev to %d.%d\n", HW_REV_MAJOR, HW_REV_MINOR);
276 putstr("\nFactory Test TXRX\n");
277 print_mac_addr(ethernet_mac_addr()->addr);
280 ethernet_register_link_changed_callback(link_changed_callback);
285 // make bit 15 of Tx gpio's be a s/w output
286 hal_gpio_set_sel(GPIO_TX_BANK, 15, 's');
287 hal_gpio_set_ddr(GPIO_TX_BANK, 0x8000, 0x8000);
290 output_regs->debug_mux_ctrl = 1;
292 hal_gpio_set_sels(GPIO_TX_BANK, "1111111111111111");
293 hal_gpio_set_sels(GPIO_RX_BANK, "1111111111111111");
294 hal_gpio_set_ddr(GPIO_TX_BANK, 0xffff, 0xffff);
295 hal_gpio_set_ddr(GPIO_RX_BANK, 0xffff, 0xffff);
299 // initialize double buffering state machine for ethernet -> DSP Tx
301 dbsm_init(&dsp_tx_sm, DSP_TX_BUF_0,
302 &dsp_tx_recv_args, &dsp_tx_send_args,
306 // initialize double buffering state machine for DSP RX -> Ethernet
309 dbsm_init(&dsp_rx_sm, DSP_RX_BUF_0,
310 &dsp_rx_recv_args, &dsp_rx_send_args,
311 fw_sets_seqno_inspector);
314 dbsm_init(&dsp_rx_sm, DSP_RX_BUF_0,
315 &dsp_rx_recv_args, &dsp_rx_send_args,
319 // tell app_common that this dbsm could be sending to the ethernet
320 ac_could_be_sending_to_eth = &dsp_rx_sm;
323 // program tx registers
326 // kick off the state machine
327 dbsm_start(&dsp_tx_sm);
332 // hal_gpio_write(GPIO_TX_BANK, which, 0x8000);
335 buffer_irq_handler(0);
337 int pending = pic_regs->pending; // poll for under or overrun
339 if (pending & PIC_UNDERRUN_INT){
340 dbsm_handle_tx_underrun(&dsp_tx_sm);
341 pic_regs->pending = PIC_UNDERRUN_INT; // clear interrupt
345 if (pending & PIC_OVERRUN_INT){
346 dbsm_handle_rx_overrun(&dsp_rx_sm);
347 pic_regs->pending = PIC_OVERRUN_INT; // clear pending interrupt
349 // FIXME Figure out how to handle this robustly.
350 // Any buffers that are emptying should be allowed to drain...
353 // restart_streaming();
354 // FIXME report error
357 // FIXME report error