2 * Copyright 2007,2008 Free Software Foundation, Inc.
4 * This program is free software: you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation, either version 3 of the License, or
7 * (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
14 * You should have received a copy of the GNU General Public License
15 * along with this program. If not, see <http://www.gnu.org/licenses/>.
23 #include "memory_map.h"
26 #include "buffer_pool.h"
31 #include "usrp2_eth_packet.h"
33 #include "app_passthru_v2.h"
34 #include "memcpy_wa.h"
41 #define FW_SETS_SEQNO 1 // define to 0 or 1 (FIXME must be 1 for now)
44 static int fw_seqno __attribute__((unused)); // used when f/w is filling in sequence numbers
49 * Full duplex Tx and Rx between ethernet and serdes
51 * Buffer 1 is used by the cpu to send frames to the host.
52 * Buffers 2 and 3 are used to double-buffer the DSP Rx to eth flow
53 * Buffers 4 and 5 are used to double-buffer the eth to DSP Tx eth flow
55 //#define CPU_RX_BUF 0 // eth -> cpu
57 #define DSP_RX_BUF_0 2 // serdes -> eth (double buffer)
58 #define DSP_RX_BUF_1 3 // serdes -> eth
59 #define DSP_TX_BUF_0 4 // eth -> serdes (double buffer)
60 #define DSP_TX_BUF_1 5 // eth -> serdes
63 * ================================================================
64 * configure serdes double buffering state machine (eth -> serdes)
65 * ================================================================
69 // Receive from ethernet
70 buf_cmd_args_t dsp_tx_recv_args = {
77 buf_cmd_args_t dsp_tx_send_args = {
80 0 // filled in from last_line register
83 dbsm_t dsp_tx_sm; // the state machine
86 * ====================================================================
87 * configure serdes RX double buffering state machine (serdes -> eth)
88 * ====================================================================
91 // receive from serdes
92 buf_cmd_args_t dsp_rx_recv_args = {
99 buf_cmd_args_t dsp_rx_send_args = {
101 0, // starts with ethernet header in line 0
102 0, // filled in from list_line register
105 dbsm_t dsp_rx_sm; // the state machine
108 // The mac address of the host we're sending to.
109 u2_mac_addr_t host_mac_addr;
112 // ----------------------------------------------------------------
117 * Debugging ONLY. This will be handled by the tx_protocol_engine.
119 * This is called when the DSP Rx chain has filled in a packet.
120 * We set and increment the seqno, then return false, indicating
121 * that we didn't handle the packet. A bit of a kludge
122 * but it should work.
126 fw_sets_seqno_inspector(dbsm_t *sm, int buf_this) // returns false
129 uint32_t *p = buffer_ram(buf_this);
130 uint32_t last_line = buffer_pool_status->last_line[buf_this] - sm->last_line_adj;
131 printf("fw_sets_seqno_inspector: buf_this = %d, last_line = %d\n",
132 buf_this, last_line);
134 print_buffer(p, (last_line + 1));
138 uint32_t *p = buffer_ram(buf_this);
139 uint32_t seqno = fw_seqno++;
141 // KLUDGE all kinds of nasty magic numbers and embedded knowledge
143 t = (t & 0xffff00ff) | ((seqno & 0xff) << 8);
147 return false; // we didn't handle the packet
153 buffer_irq_handler(unsigned irq)
155 uint32_t status = buffer_pool_status->status;
157 if (0 && (status & ~BPS_IDLE_ALL)){
162 dbsm_process_status(&dsp_tx_sm, status);
163 dbsm_process_status(&dsp_rx_sm, status);
171 output_regs->led_src = 0x3; // h/w controls bottom two bits
172 clocks_enable_test_clk(true, 1);
174 putstr("\neth <-> serdes\n");
176 ethernet_register_link_changed_callback(link_changed_callback);
179 // clocks_mimo_config(MC_WE_LOCK_TO_SMA | MC_PROVIDE_CLK_TO_MIMO);
180 clocks_mimo_config(MC_WE_DONT_LOCK | MC_PROVIDE_CLK_TO_MIMO);
183 // make bit 15 of Tx gpio's be a s/w output
184 hal_gpio_set_sel(GPIO_TX_BANK, 15, 's');
185 hal_gpio_set_ddr(GPIO_TX_BANK, 0x8000, 0x8000);
189 output_regs->debug_mux_ctrl = 1;
190 hal_gpio_set_sels(GPIO_TX_BANK, "1111111111111111");
191 hal_gpio_set_sels(GPIO_RX_BANK, "1111111111111111");
192 hal_gpio_set_ddr(GPIO_TX_BANK, 0xffff, 0xffff);
193 hal_gpio_set_ddr(GPIO_RX_BANK, 0xffff, 0xffff);
197 // initialize double buffering state machine for ethernet -> serdes
199 dbsm_init(&dsp_tx_sm, DSP_TX_BUF_0,
200 &dsp_tx_recv_args, &dsp_tx_send_args,
204 // initialize double buffering state machine for serdes -> ethernet
207 dbsm_init(&dsp_rx_sm, DSP_RX_BUF_0,
208 &dsp_rx_recv_args, &dsp_rx_send_args,
209 fw_sets_seqno_inspector);
212 dbsm_init(&dsp_rx_sm, DSP_RX_BUF_0,
213 &dsp_rx_recv_args, &dsp_rx_send_args,
217 // tell app_common that this dbsm could be sending to the ethernet
218 ac_could_be_sending_to_eth = &dsp_rx_sm;
221 // kick off the state machines
222 dbsm_start(&dsp_tx_sm);
223 dbsm_start(&dsp_rx_sm);
228 // hal_gpio_write(GPIO_TX_BANK, which, 0x8000);
231 buffer_irq_handler(0);