2 * Copyright 2007,2008 Free Software Foundation, Inc.
4 * This program is free software: you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation, either version 3 of the License, or
7 * (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
14 * You should have received a copy of the GNU General Public License
15 * along with this program. If not, see <http://www.gnu.org/licenses/>.
23 #include "memory_map.h"
26 #include "buffer_pool.h"
31 #include "usrp2_eth_packet.h"
33 #include "app_common.h"
34 #include "print_rmon_regs.h"
42 * receive packets from ethernet at a fixed rate and discard them
45 int total_rx_pkts = 0;
46 int total_rx_bytes = 0;
49 static int timer_delta = (int)(MASTER_CLK_RATE * 10e-6); // 10us / tick
53 * This program can respond to queries from the host
54 * and stream rx samples.
56 * Buffer 1 is used by the cpu to send frames to the host.
57 * Buffers 2 and 3 are used to double-buffer the DSP Rx to eth flow
58 * Buffers 4 and 5 are used to double-buffer the eth to DSP Tx eth flow
60 //#define CPU_RX_BUF 0 // eth -> cpu
61 //#define CPU_TX_BUF 1 // cpu -> eth
63 #define DSP_RX_BUF_0 2 // dsp rx -> eth (double buffer)
64 #define DSP_RX_BUF_1 3 // dsp rx -> eth
65 #define DSP_TX_BUF_0 4 // eth -> dsp tx (double buffer)
66 #define DSP_TX_BUF_1 5 // eth -> dsp tx
70 // ----------------------------------------------------------------
73 // The mac address of the host we're sending to.
74 u2_mac_addr_t host_mac_addr;
77 static volatile bool receive_packet_now = false;
80 timer_irq_handler(unsigned irq)
82 hal_set_timeout(timer_delta); // schedule next timeout
83 receive_packet_now = true;
89 underrun_irq_handler(unsigned irq)
96 start_rx_cmd(const u2_mac_addr_t *host, op_start_rx_t *p)
108 dsp_tx_regs->clear_state = 1;
109 bp_clear_buf(DSP_TX_BUF_0);
110 bp_clear_buf(DSP_TX_BUF_1);
115 op_config_tx_t def_config;
116 memset(&def_config, 0, sizeof(def_config));
117 def_config.phase_inc = 408021893; // 9.5 MHz [2**32 * fc/fsample]
118 def_config.scale_iq = (tx_scale << 16) | tx_scale;
119 def_config.interp = interp;
122 config_tx_cmd(&def_config);
127 * Called when an ethernet packet is received.
129 * Claim that we handled all the packets,
130 * dropping those destined for the TX DSP chain
134 nop_eth_pkt_inspector(dbsm_t *sm, int bufno)
136 hal_toggle_leds(0x1);
138 u2_eth_packet_t *pkt = (u2_eth_packet_t *) buffer_ram(bufno);
139 size_t byte_len = (buffer_pool_status->last_line[bufno] - 1) * 4;
142 total_rx_bytes += byte_len;
144 // inspect rcvd frame and figure out what do do.
146 if (pkt->ehdr.ethertype != U2_ETHERTYPE)
147 return true; // ignore, probably bogus PAUSE frame from MAC
149 int chan = u2p_chan(&pkt->fixed);
153 handle_control_chan_frame(pkt, byte_len);
154 return true; // we handled the packet
159 return true; // We handled the data by dropping it :)
166 buffer_irq_handler(unsigned irq)
168 uint32_t status = buffer_pool_status->status;
170 if (status & (BPS_DONE(CPU_TX_BUF) | BPS_ERROR(CPU_TX_BUF)))
171 bp_clear_buf(CPU_TX_BUF);
173 if (status & (BPS_DONE(DSP_TX_BUF_0) | BPS_ERROR(DSP_TX_BUF_0))){
174 bp_clear_buf(DSP_TX_BUF_0);
176 if (status & BPS_ERROR(DSP_TX_BUF_0)){
177 int crc = eth_mac_read_rmon(0x05);
178 int fifo_full = eth_mac_read_rmon(0x06);
179 int too_short_too_long = eth_mac_read_rmon(0x07);
180 putstr("Errors! status = ");
183 printf("crc_err\t\t= %d\n", crc);
184 printf("fifo_full\t\t= %d\n", fifo_full);
185 printf("too_short_too_long\t= %d\n", too_short_too_long);
187 printf("total_rx_pkts = %d\n", total_rx_pkts);
188 printf("total_rx_bytes = %d\n", total_rx_bytes);
191 nop_eth_pkt_inspector(0, DSP_TX_BUF_0);
194 if (receive_packet_now && (status & BPS_IDLE(DSP_TX_BUF_0))){
195 receive_packet_now = false;
196 bp_receive_to_buf(DSP_TX_BUF_0, PORT_ETH, 1, 0, BP_LAST_LINE);
206 // setup tx gpio bits for GPIOM_FPGA_1 -- fpga debug output
207 hal_gpio_set_tx_mode(15, 0, GPIOM_FPGA_1);
208 hal_gpio_set_rx_mode(15, 0, GPIOM_FPGA_1);
210 putstr("\ntx_drop_rate_limited\n");
213 hal_set_leds(0x0, 0x3);
215 pic_register_handler(IRQ_UNDERRUN, underrun_irq_handler);
217 pic_register_handler(IRQ_TIMER, timer_irq_handler);
218 hal_set_timeout(timer_delta);
220 ethernet_register_link_changed_callback(link_changed_callback);
223 // program tx registers
226 // start a receive from ethernet
227 bp_receive_to_buf(DSP_TX_BUF_0, PORT_ETH, 1, 0, BP_LAST_LINE);
230 buffer_irq_handler(0);