2 * Copyright 2007,2008 Free Software Foundation, Inc.
4 * This program is free software: you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation, either version 3 of the License, or
7 * (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
14 * You should have received a copy of the GNU General Public License
15 * along with this program. If not, see <http://www.gnu.org/licenses/>.
23 #include "memory_map.h"
26 #include "buffer_pool.h"
31 #include "usrp2_eth_packet.h"
33 #include "app_common.h"
34 #include "print_rmon_regs.h"
41 * Like tx_only.c, but we discard data packets instead of sending them to the
45 int total_rx_pkts = 0;
46 int total_rx_bytes = 0;
49 static int timer_delta = MASTER_CLK_RATE/1000; // tick at 1kHz
52 * This program can respond to queries from the host
53 * and stream rx samples.
55 * Buffer 1 is used by the cpu to send frames to the host.
56 * Buffers 2 and 3 are used to double-buffer the DSP Rx to eth flow
57 * Buffers 4 and 5 are used to double-buffer the eth to DSP Tx eth flow
59 //#define CPU_RX_BUF 0 // eth -> cpu
60 //#define CPU_TX_BUF 1 // cpu -> eth
62 #define DSP_RX_BUF_0 2 // dsp rx -> eth (double buffer)
63 #define DSP_RX_BUF_1 3 // dsp rx -> eth
64 #define DSP_TX_BUF_0 4 // eth -> dsp tx (double buffer)
65 #define DSP_TX_BUF_1 5 // eth -> dsp tx
69 * ================================================================
70 * configure DSP RX double buffering state machine
71 * ================================================================
74 // 4 lines of ethernet hdr + 1 line (word0)
75 // DSP Rx writes timestamp followed by nlines_per_frame of samples
76 #define DSP_RX_FIRST_LINE 5
77 #define DSP_RX_SAMPLES_PER_FRAME 128
78 #define DSP_RX_EXTRA_LINES 1 // writes timestamp
80 // Receive from DSP Rx
81 buf_cmd_args_t dsp_rx_recv_args = {
88 buf_cmd_args_t dsp_rx_send_args = {
90 0, // starts with ethernet header in line 0
91 0, // filled in from last_line register
94 dbsm_t dsp_rx_sm; // the state machine
97 * ================================================================
98 * configure DSP TX double buffering state machine
99 * ================================================================
102 // 4 lines of ethernet hdr + 2 lines (word0 + timestamp)
103 // DSP Tx reads word0 (flags) + timestamp followed by samples
105 #define DSP_TX_FIRST_LINE 4
106 #define DSP_TX_SAMPLES_PER_FRAME 250 // not used except w/ debugging
107 #define DSP_TX_EXTRA_LINES 2 // reads word0 + timestamp
109 // Receive from ethernet
110 buf_cmd_args_t dsp_tx_recv_args = {
117 buf_cmd_args_t dsp_tx_send_args = {
119 DSP_TX_FIRST_LINE, // starts just past ethernet header
120 0 // filled in from last_line register
123 dbsm_t dsp_tx_sm; // the state machine
126 // ----------------------------------------------------------------
129 // The mac address of the host we're sending to.
130 u2_mac_addr_t host_mac_addr;
134 timer_irq_handler(unsigned irq)
136 hal_set_timeout(timer_delta); // schedule next timeout
141 underrun_irq_handler(unsigned irq)
145 dbsm_stop(&dsp_tx_sm);
146 dsp_tx_regs->clear_state = 1;
147 dbsm_start(&dsp_tx_sm); // restart sm so we're listening to ethernet again
149 // putstr("\nirq: underrun\n");
154 start_rx_cmd(const u2_mac_addr_t *host, op_start_rx_t *p)
166 dsp_tx_regs->clear_state = 1;
167 bp_clear_buf(DSP_TX_BUF_0);
168 bp_clear_buf(DSP_TX_BUF_1);
174 op_config_tx_t def_config;
175 memset(&def_config, 0, sizeof(def_config));
176 def_config.phase_inc = 408021893; // 9.5 MHz [2**32 * fc/fsample]
177 def_config.scale_iq = (tx_scale << 16) | tx_scale;
178 def_config.interp = interp;
181 config_tx_cmd(&def_config);
187 buffer_irq_handler(unsigned irq)
189 uint32_t status = buffer_pool_status->status;
191 if (status & BPS_ERROR_ALL){
192 // FIXME rare path, handle error conditions
193 putstr("Errors! status = ");
196 printf("total_rx_pkts = %d\n", total_rx_pkts);
197 printf("total_rx_bytes = %d\n", total_rx_bytes);
201 if (status & (BPS_ERROR(DSP_TX_BUF_0) | BPS_ERROR(DSP_TX_BUF_1))){
202 dbsm_stop(&dsp_tx_sm);
203 dsp_tx_regs->clear_state = 1; // try to restart
204 dbsm_start(&dsp_tx_sm);
209 dbsm_process_status(&dsp_tx_sm, status);
211 if (status & BPS_DONE(CPU_TX_BUF)){
212 bp_clear_buf(CPU_TX_BUF);
217 * Called when an ethernet packet is received.
218 * Return true if we handled it here (always!)
221 nop_eth_pkt_inspector(dbsm_t *sm, int bufno)
223 hal_toggle_leds(0x1);
225 u2_eth_packet_t *pkt = (u2_eth_packet_t *) buffer_ram(bufno);
226 size_t byte_len = (buffer_pool_status->last_line[bufno] - 1) * 4;
229 total_rx_bytes += byte_len;
231 // inspect rcvd frame and figure out what do do.
233 if (pkt->ehdr.ethertype != U2_ETHERTYPE)
234 return true; // ignore, probably bogus PAUSE frame from MAC
236 int chan = u2p_chan(&pkt->fixed);
240 handle_control_chan_frame(pkt, byte_len);
241 return true; // we handled the packet
246 return true; // say we handled it
257 // setup tx gpio bits for GPIOM_FPGA_1 -- fpga debug output
258 hal_gpio_set_tx_mode(15, 0, GPIOM_FPGA_1);
259 hal_gpio_set_rx_mode(15, 0, GPIOM_FPGA_1); // no printing...
261 putstr("\ntx_drop2\n");
264 hal_set_leds(0x0, 0x3);
266 // pic_register_handler(IRQ_OVERRUN, overrun_irq_handler);
267 pic_register_handler(IRQ_UNDERRUN, underrun_irq_handler);
269 //pic_register_handler(IRQ_TIMER, timer_irq_handler);
270 //hal_set_timeout(timer_delta);
272 ethernet_register_link_changed_callback(link_changed_callback);
276 // initialize double buffering state machine for ethernet -> DSP Tx
278 dbsm_init(&dsp_tx_sm, DSP_TX_BUF_0,
279 &dsp_tx_recv_args, &dsp_tx_send_args,
280 nop_eth_pkt_inspector);
282 // program tx registers
285 // kick off the state machine
286 dbsm_start(&dsp_tx_sm);
289 buffer_irq_handler(0);